Implementing FIFOs Using Built-in Control Logic (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Built-in FIFO control logic, available in the block memory of some FPGA hardware targets, saves a significant amount of FPGA resources. In addition, these dedicated circuits can support higher clock rates than control logic you create using slice fabric.

Note  Refer to Xilinx documentation for information about the properties of the FPGA on your target hardware.

Restrictions and Caveats for Using Built-In FIFO Control Logic

The following list outlines the restrictions and caveats for using built-in FIFOs.

  • FPGAs must have a dedicated FIFO controller inside each block memory.
  • The clock domains for built-in FIFOs must have stable and free-running clocks.
  • (Xilinx Vivado) The following methods do not support FIFOs with the built-in control logic:
  • Using the following methods increases resource usage and reduces the maximum frequencies of clock domains for reading and/or writing:
  • Using the Clear method takes multiple clock cycles because it clears elements one by one instead of simultaneously.
  • On some targets, built-in and target-optimal FIFO control logic are not supported in simulation exports. You can use Conditional Disable structures to implement slice-fabric FIFO control logic for simulation exports.
  • Enabling the handshaking interface on the Write method increases FIFO depth by one.
  • Once a built-in FIFO is completely full, you must wait until there are at least two empty elements before writing to the FIFO. The Get Number of Elements to Write method and the Write (FIFO Method) indicate that the FIFO is full until there are at least two empty elements.
  • The calculation for the coerced Requested Number of Elements varies depending on FPGA families.

Optimizing FIFO Control Logic Using the Target Optimal Option

If you want to use built-in FIFOs but cannot guarantee that the application will meet all restrictions for using built-in FIFOs, you can configure the FIFO to use the optimal configuration for the situation. On the General page of the FIFO Properties dialog box, select Target Optimal from the Control Logic pull-down menu.

The Target Optimal option switches the FIFO configuration between Slice Fabric and Built-in logic depending upon the capabilities of the target and the application. The application uses built-in FIFOs when the target supports built-in FIFOs and the clock domain does not stop during reset. Otherwise, the application uses slice fabric to create the control logic.

Note  Selecting Target Optimal means that the actual number of elements in the FIFO changes depending upon the target and placement of the FIFO in the application. The value of Actual Number of Elements is always greater than or equal to the value of Requested Number of Elements.

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