|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Built-in FIFO control logic, available in the block memory of some FPGA hardware targets, saves a significant amount of FPGA resources. In addition, these dedicated circuits can support higher clock rates than control logic you create using slice fabric.
|Note Refer to Xilinx documentation for information about the properties of the FPGA on your target hardware.|
The following list outlines the restrictions and caveats for using built-in FIFOs.
If you want to use built-in FIFOs but cannot guarantee that the application will meet all restrictions for using built-in FIFOs, you can configure the FIFO to use the optimal configuration for the situation. On the General page of the FIFO Properties dialog box, select Target Optimal from the Control Logic pull-down menu.
The Target Optimal option switches the FIFO configuration between Slice Fabric and Built-in logic depending upon the capabilities of the target and the application. The application uses built-in FIFOs when the target supports built-in FIFOs and the clock domain does not stop during reset. Otherwise, the application uses slice fabric to create the control logic.
|Note Selecting Target Optimal means that the actual number of elements in the FIFO changes depending upon the target and placement of the FIFO in the application. The value of Actual Number of Elements is always greater than or equal to the value of Requested Number of Elements.|