Choosing between the FIFO Implementation Options (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Understanding the available FIFO implementation options can help you create more efficient FPGA designs. The FIFO implementation options specify how the FPGA represents target-scoped and VI-defined FIFOs in hardware. Use the FIFO Properties dialog box to select a FIFO implementation option.

Note  DMA and peer-to-peer FIFOs always use block memory.

The following table helps you determine which FIFO implementation best suits your application.

Implementation What Does It Do? What Considerations Should I Keep in Mind?
Flip-Flops Flip-flops are FPGA resources that you can use for data storage or other tasks, such as addition and subtraction. For this reason, flip-flops are often the least abundant FPGA resource for moving or storing data. You cannot use FIFOs implemented using flip-flops across multiple clock domains.
Look-up Tables (LUTs) Look-up tables, also known as distributed RAM, consist of logic gates hard-wired on the FPGA. Like flip-flops, LUTs can function as FPGA resources. You cannot use FIFOs implemented using look-up tables across multiple clock domains.
Block Memory Block memory, also known as block random access memory, block RAM or BRAM, is a dedicated FPGA resource for data storage. Refer to Implementing Block Memory FIFOs for more information about using built-in control logic with a block memory implementation. If you configure a target-scoped or VI-defined FIFO using block memory, you can configure the control logic. DMA and peer-to-peer FIFOs can use only block memory. If you select the Block Memory option, you might not be able to read data in a target-scoped or VI-defined FIFO until up to six clock cycles after you write the data to the FIFO. If you select the timeout interface, wire the Timed Out? output of the FIFO Method Node configured with the Read method to determine whether the upstream data is ready. If you select the handshaking interface, wire the Output Valid output of the FIFO Method Node configured with the Read method to determine whether the upstream data is ready.

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