Integrating Third-Party IP (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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You can use two methods to integrate third-party IP into FPGA VIs: the component-level IP (CLIP) interface and the IP Integration Node. This topic compares each method to help you decide which works better for your FPGA application.

Supported IP File Types

You can use third-party IP defined using:

• VHDL
• Verilog
• Netlist files
• Xilinx IP configuration files: (Xilinx ISE) .xco files or (Xilinx Vivado) .xci files

Refer to the CLIP Interface and IP Integration Node Details section for more information about supported file types for the CLIP interface and the IP Integration Node.

Note  To import Verilog files or a large file hierarchy, you first need to compile this IP to a netlist file.

Xilinx IP

Xilinx provides and maintains the Xilinx IP. LabVIEW uses the IP Integration Node to incorporate Xilinx IP into an FPGA VI. Because Xilinx may deprecate IP cores from older releases, NI only can guarantee support in the IP Integration Node for Xilinx IP configuration files created using the current version of the Xilinx compilation tools for your FPGA target. Refer to the support document at ni.com for more information about NI hardware supported by each Xilinx compilation tool.

Note  Xilinx licenses the Xilinx IP. You can find the licensing information in the Context Help window for a specific Xilinx IP. To import a license, place the .lic file in one of the following default directories, depending on your specific FPGA target: (Xilinx ISE) C:\NIFPGA\programs\XilinxY_Z\ISE\coregen\core_licenses, where XilinxY_Z is the current version of the Xilinx compilation tool for ISE for your FPGA target. (Xilinx Vivado) C:\NIFPGA\programs\VivadoA_B\data\ip\core_licenses, where VivadoA_B is the current version of the Xilinx compilation tool for Vivado for your FPGA target.

(Xilinx ISE) NI installs the Xilinx IP generator, coregen.exe, in the same directory as LabVIEW.exe. By default, the Xilinx IP generator is located in the C:\NIFPGA\programs\XilinxY_Z\ISE\bin\nt directory, where XilinxY_Z is the current version of the Xilinx compilation tool for ISE for your FPGA target.

If you migrate Xilinx IP from one FPGA target to another or from one version of LabVIEW to another, you may have to regenerate the IP on the new target.

CLIP Interface and IP Integration Node Details

The following table compares the two methods of integrating third-party IP in more detail.

	CLIP	IP Integration Node
Supported execution modes	Outside the single-cycle Timed Loop Inside the single-cycle Timed Loop	Inside the single-cycle Timed Loop
Support for simulation
Support for third-party simulation
Supported LabVIEW data type Note  Top-level VHDL files support only the std_logic and std_logic_vector port types.	Boolean Integer Fixed-point Note  CLIP sockets for certain FPGA hardware targets support the Boolean array data type. Refer to the target hardware documentation for information about CLIP socket support.	Boolean Boolean array Integer Fixed-point Single-precision floating-point
Supported synthesis file formats Note  Supported synthesis file formats depend on your specific FPGA target and are included in the compilation. Synthesis files of unsupported file formats are not included in the compilation, and adding them may cause unexpected behavior. Refer to the support document at ni.com for more information about NI hardware supported by each Xilinx compilation tool.	(Xilinx ISE) .vhd, .coe, .data, .vhe, .bmm netlist: .ngc, .edif, .edn, .edf, .ncd constraints: .ucf Xilinx IP configuration: .xco (Xilinx Vivado) .vhd, .coe, .data, .vhe, .bmm netlist: .ngc, .edif, .edn, .edf, .ncd, .dcp constraints: .xdc Xilinx IP configuration: .xci Note  You only can use .vhd files as top-level synthesis files.	(Xilinx ISE) .vhd, .coe, .data, .vhe, .bmm netlist: .ngc, .edif, .edn, .edf, .ncd Xilinx IP configuration: .xco (Xilinx Vivado) .vhd, .coe, .data, .vhe, .bmm netlist: .ngc, .edif, .edn, .edf, .ncd, .dcp Xilinx IP configuration: .xci
Execution model	Executes parallel to, and independent of, the data flow of an FPGA VI	Executes as defined by the data flow of an FPGA VI
Place of declaration and behavior	Declared in a LabVIEW project; acts as a global	Declared locally in an FPGA VI
Support for multiple clock domains	Maximum number of clocks defined by FPGA	Maximum of two clocks: an SCTL clock and an FPGA-derived clock, where the derived clock executes at a rate that is an integer multiple of the SCTL clock
Support for accessing clocks from the IP as clocks for a single-cycle Timed Loop
Support for VHDL generics
Support for constraints on IP	On specific FPGA targets, you can specify constraints in the CLIP interface using the (Xilinx ISE) Xilinx Foundation user-constraint file (.ucf) file format or the (Xilinx Vivado) .xdc file format. However, if you apply a constraint to a CLIP signal, the LabVIEW block diagram must use that signal or LabVIEW returns a Xilinx error when you compile the VI.
Support for accessing FPGA I/O

Related Information

Using VHDL Code as Component-Level IP

IP Integration Node

Integrating Xilinx IP into FPGA VIs