Synchronizing the FPGA and the Host (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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The FPGA VI and the host VI are inherently asynchronous. If you need to synchronize execution or data transfer between the FPGA VI and the host VI, you can use interrupt-based or polling-based methods. Use interrupt-based synchronization when you need to minimize usage of the host processor and polling-based synchronization when you need lower latency. DMA FIFOs are a special kind of polling-based synchronization that you can use to transfer data between the FPGA and the host. The following table summarizes the characteristics of these synchronization methods.

Synchronization Method Latency Host CPU Usage Common Use
Interrupt-Based Higher Lower Datalogging
Polling-Based Lower Higher Control, Simulation
DMA FIFOs Lower Lower Datalogging

Interrupt-Based Synchronization

An interrupt is a physical hardware line to the host that the FPGA target asserts. You can use interrupts to notify the host VI of events, such as data becoming available, an error occurring, or a task finishing.

An advantage of using interrupt-based communication instead of polling-based communication is that the host VI can perform other operations while waiting for the interrupt. However, the overhead required to process the interrupt increases latency relative to polling-based synchronization.

Use the Interrupt VI to generate any of the 32 logical interrupts available on the FPGA target. Each logical interrupt specifies the reason for causing the interrupt and allows you to handle it differently in software. You can set the Interrupt VI to wait until the host VI acknowledges the interrupt on the FPGA target by wiring the Wait Until Cleared input. In this case, the Interrupt VI waits until the host VI controlling the device acknowledges the interrupt.

Use caution when you include simultaneous interrupt calls on the FPGA target. The interrupt line becomes a shared resource if you use more than one, which can induce jitter.

Polling-Based Synchronization

Polling-based synchronization involves using a loop to continually check the status of the FPGA VI and performing an action when a certain condition becomes true. You can use the timing VIs to determine the frequency of the polling loop. You can decrease the synchronization latency by increasing the frequency of the polling loop. You can decrease the host CPU usage by decreasing the frequency of the polling loop.

Direct Memory Access (DMA) and Synchronization

DMA FIFOs are inherently synchronous. The DMA engine automatically polls the status of the DMA FIFO and initiates data transfer when the DMA FIFO contains the number of data values you specify. However, you can specify the manner in which a device retrieves data from a DMA FIFO. Specifically, you can use polling-based methods to retrieve data from a DMA FIFO.


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