Interfaces Page (FIFO Properties Dialog Box)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

In the FIFO Properties dialog box, select Interfaces from the Category list to display this page.

Use this page to configure the arbitration options and the number of elements that the FPGA VI can read or write to the DMA FIFO in each clock cycle.

This page includes the following components:

  • Arbitration for Read—Sets the type of arbitration for reading from the FIFO item. Select Arbitrate if Multiple Requestors Only or Never Arbitrate if you use the FIFO Method Node in a single-cycle Timed Loop.
  • Number of Elements per Read—Specifies the number of elements that the FPGA VI can read from the DMA FIFO each clock cycle. The default is 1.
    Note  Support for configurable numbers of elements in FIFOs varies by target. Refer to your target hardware documentation for more information.
  • Arbitration for Write—Sets the type of arbitration for writing to the FIFO item. Select Arbitrate if Multiple Requestors Only or Never Arbitrate if you use the FIFO Method Node in a single-cycle Timed Loop.
  • Number of Elements per Write—Specifies the number of elements that the FPGA VI can write to the DMA FIFO each clock cycle. The default is 1.
    Note  Support for configurable numbers of elements in FIFOs varies by target. Refer to your target hardware documentation for more information.

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