General Page (FIFO Properties Dialog Box)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

In the FIFO Properties dialog box, select General from the Category list to display this page.

Use this page to edit properties for FIFOs.

This page includes the following components:

  • Name—Specifies the name of the FIFO that appears in the Project Explorer window or in the VI-Defined FIFO Configuration node. The name also appears in the FIFO Method Node on the block diagram, and you can use it in FIFO name controls and constants to access target-scoped FIFOs.
  • Type—Specifies the type of FIFO to use. This option is not available for VI-defined FIFOs.
    • Target-Scoped—FIFOs can transfer data within the FPGA VI as well as between FPGA VIs under the same target in the Project Explorer window.
    • Host to Target - DMA or Target to Host - DMADMA FIFOs can transfer data between the host VI and target.
    • Peer to Peer Writer or Peer to Peer Reader—FIFOs can transfer data using a peer-to-peer stream.
  • Disable on Overflow—Specifies to disable the peer-to-peer stream when the writer FIFO attempts to write to the stream and fails. This option is only available for peer-to-peer writer FIFOs.
  • Disable on Underflow—Specifies to disable the peer-to-peer stream when the reader FIFO does not receive data from the stream. This option is only available for peer-to-peer reader FIFOs.
  • Requested Number of Elements—Specifies the desired number of elements the FIFO can hold. The maximum number of elements the FIFO can hold depends on the Implementation you select and the amount of resources available on the FPGA for the Implementation. If the FIFO uses built-in control logic, the maximum number of elements also depends on the data type. The width of the built-in FIFO must be less than or equal to 1024.

    If the FPGA does not have enough resources for the Requested Number of Elements you enter, the FPGA VI fails to compile. If you select Host to Target - DMA or Target to Host - DMA in the Type pull-down menu, Requested Number of Elements specifies the size of the FPGA FIFO of the DMA channel. Maximum DMA FIFO size varies by target. Refer to the specific FPGA target hardware documentation for more information about DMA FIFO size limitations.

    If you select Block Memory in the Implementation control, restrictions apply to the number of elements the FIFO can hold. Actual Number of Elements indicates the number of elements in the FIFO, which may not be the same as Requested Number of Elements.
    Note  If you experience timeout during DMA transfers from the FPGA to a host, use the FIFO.Configure method of the Invoke Method function and increase the Depth parameter rather than increasing the Requested Number of Elements. Increasing the Depth parameter increases the size of the host-side buffer, which is more likely to resolve the timeout and does not increase FPGA device utilization.
  • Implementation—Specifies the type of storage the FIFO uses on the FPGA. You can specify the implementation only for target-scoped and VI-defined FIFOs. Contains the following options:
    • Flip-Flops—Stores the data in flip-flops available on the FPGA and provides the fastest performance. NI recommends using this option for small FIFOs, up to 100 bytes. You cannot use FIFOs with an Implementation of Flip-Flops or Look-Up Table across multiple clock domains.
    • Look-Up Table—Stores the data in look-up tables available on the FPGA. Xilinx literature describes this implementation as distributed RAM or LUT RAM. NI recommends using this option for FIFOs that are 100–300 bytes. You cannot use FIFOs with an Implementation of Flip-Flops or Look-Up Table across multiple clock domains.
    • Block Memory—Stores the data using embedded blocks of memory. Xilinx literature describes this implementation as block RAM or BRAM. NI recommends using this option for FIFOs larger than 300 bytes.
      Note  If you select the Block Memory option, you might not be able to read data in a target-scoped FIFO or VI-defined FIFO until up to six clock cycles after you write the data to the FIFO. If you select the timeout interface, use the Timed Out? output of the FIFO Method Node that invokes the Read method to determine when the upstream data is ready. If you select the handshaking interface, use the Output Valid output of the FIFO Method Node that invokes the Read method to determine whether the upstream data is ready.
    All of the above implementation options contain the following components:
    • Actual Number of Elements—Returns the configured number of elements. Sometimes the requested number of elements is not compatible with the FIFO configuration. In this case, LabVIEW coerces the requested number of elements to a compatible number and Actual Number of Elements returns this number.

      If you select the built-in or target-optimal control logic, Actual Number of Elements might return multiple numbers. Interpret these numbers in the following ways:
      • Built-InActual Number of Elements returns two numbers, which LabVIEW uses when the handshaking interface is disabled or enabled, respectively.
        Note  (Xilinx Vivado) The actual number of elements in the FIFO is unknown at configuration time. Actual Number of Elements returns only one number, which is the closest power of two, greater than Requested Number of Elements. This number is a minimum guaranteed number, which might be smaller than the actual number of elements in the FIFO.
      • Target-Optimal—LabVIEW implements the FIFO using either slice fabric or built-in control logic, depending on the clock domain and target type. Actual Number of Elements returns two or three numbers: the first one for the slice fabric control logic and the other(s) for the built-in control logic.
    • Control Logic—Specifies how the FPGA implements the FIFO.

      • Slice Fabric—Specifies that the FPGA uses flip-flops, LUTs, and block memory to implement the control logic for the FIFO.
      • Target Optimal—Specifies that the FPGA uses built-in FIFO control logic or slice fabric control logic, depending on the target and application.
      • Built-In—Specifies that the FPGA uses built-in FIFO control logic. Not all FPGAs support built-in FIFO control logic and restrictions apply.
        Note  (Xilinx Vivado) If you select the built-in control logic, you cannot use this FIFO with the Get Number of Elements to Read or Get Number of Elements to Write method because the actual number of elements in the FIFO is unknown at configuration time. In simulation mode, the Timed Out? output value of the Read or Write method might not reflect the actual behavior on hardware because these methods use the conservative number in Actual Number of Elements as the FIFO depth, which might be smaller than the actual number of elements in the FIFO.

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