Creating FIFOs in FPGA VIs (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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LabVIEW provides different types of FIFOs that enable you to transfer data between different portions of an FPGA VI, between VIs in an FPGA target, or between devices. You can create FIFOs from the Project Explorer window or, in the case of target-scoped and VI-defined FIFOs, directly from the block diagram.

Creating a Target-Scoped FIFO from the Project Explorer Window

Complete the following steps to create a target-scoped FIFO from the Project Explorer window.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select New»FIFO to display the FIFO Properties dialog box.
  3. On the General page, expand the pull-down menu under Implementation to display the available options.
  4. Click OK to finish creating the FIFO.
  5. Drag the FIFO from the Project Explorer window to the block diagram. LabVIEW adds a FIFO Method node configured for the FIFO.

Creating a FIFO from the Block Diagram

You can create either a target-scoped or a VI-defined FIFO from the block diagram.

Target-Scoped:

  1. Display the block diagram.
  2. From the Functions palette, add a FIFO Method Node to the block diagram. 

  3. Right-click the FIFO Method node and select Add New FIFO from the shortcut menu to display the FIFO Properties dialog box.
    Tip  You also can right-click the FIFO Method Node and select Select FIFO»x from the shortcut menu, where x is an existing FIFO.
  4. On the General page, expand the Implementation pull-down menu to display the available options.
  5. Click OK to finish creating the FIFO.

You also can wire a FIFO Constant, FIFO Method Node, or VI-Defined FIFO Configuration node to the FIFO In input to specify the FIFO. LabVIEW configures the FIFO Method Node with the default method. For FIFOs that support the Write method, the default method is Write. To select a different method after you specify the FIFO, right-click the FIFO Method Node and select Select Method»y from the shortcut menu, where y is the specific method.

VI-Defined:

  1. Display the block diagram.
  2. From the Functions palette, add a VI-Defined FIFO Configuration Node to the block diagram. 

  3. Right click the VI-Defined FIFO Configuration node and select Configure from the shortcut menu to display the FIFO Properties dialog box.
  4. On the General page, expand the Implementation pull-down menu to display the available options.
  5. Click OK to finish creating the FIFO.

Creating a DMA FIFO from the Project Explorer Window

First, complete the following steps to determine whether your target supports DMA FIFOs.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select Properties from the shortcut menu to display the FPGA Target Properties dialog box.
  3. Refer to the Target Information box on the General page to find DMA support information. If your target supports DMA, the Target Information box gives the number of DMA channels. If your target does not support DMA, the Target Information box indicates that DMA is not supported.

If your target supports DMA FIFOs, complete the following steps to create a DMA FIFO in an FPGA VI. Refer to Reading DMA FIFOs from Host VIs and Writing to DMA FIFOs from Host VIs for help configuring a host VI to read and write DMA FIFOs.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select New»FIFO to display the FIFO Properties dialog box.
  3. Use the Type pull-down menu to select either Host to Target—DMA or Target to Host—DMA, depending on which direction you want to stream the data.
  4. Click OK to finish creating the FIFO.
  5. Drag the FIFO from the Project Explorer window to the block diagram. LabVIEW adds a FIFO Method node configured for the FIFO.

Creating a Peer-to-Peer FIFO from the Project Explorer Window

Complete the following steps to create a peer-to-peer FIFO from the Project Explorer window or to determine whether a particular target supports peer-to-peer streaming.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select New»FIFO to display the FIFO Properties dialog box.
  3. On the General page, select Peer to Peer Writer or Peer to Peer Reader from the Type pull-down menu. If these options are not available in the pull-down menu, the target does not support peer-to-peer FIFOs.
  4. Click OK to finish creating the FIFO.

Refer to the topics on using peer-to-peer streaming with FPGA targets for information about how to use peer-to-peer FIFOs.

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