|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Complete the following steps to run an FPGA VI on the host computer.
|Note If an FPGA VI uses I/O variables, you cannot execute that FPGA VI on the host computer. If you place an I/O Variable node on the block diagram of an FPGA VI on the host computer, LabVIEW breaks the Run button.|
|Note Selecting Use Simulated I/O is not compatible with CLIP.|
|Tip You also can change where the FPGA VI executes by right-clicking the FPGA target in the Project Explorer window and selecting an option from the Select Execution Mode shortcut menu.|
You can use a host VI to communicate with an FPGA VI executing in simulation mode using simulated I/O. However, you must be aware of special considerations when using the host VI.
If you include a digital I/O resource in a single-cycle Timed Loop, each synchronization register introduces a delay corresponding to one iteration of the single-cycle Timed Loop. In some cases, delays outside the FPGA may be significant for the system. If accurate modeling of the delays between the LabVIEW diagram and the FPGA is important for testing the logic of the application by executing the FPGA VI on the host computer, delay simulation data for the I/O by the number of calls to the I/O node, equivalent to the number of synchronization registers.
When you debug an FPGA VI using test benches, you execute the FPGA VI on the host computer multiple times. However, FPGA VIs are subject to special considerations when compiled for an FPGA target. In addition to testing the logic of the FPGA VI, you must consider whether the FPGA VI compiles with all of the constraints enforced by the FPGA design. Design considerations include whether the application utilizes more FPGA resources than available and whether the logic meets timing constraints set by the FPGA clocks.
NI recommends that you compile the FPGA VI periodically to make sure the FPGA VI satisfies all of these requirements. In addition, you can generate intermediate files and estimate FPGA resource utilization using commands in the build specification shortcut menu. The generation of intermediate files is a relatively short step in the process, and it often reports a large percentage of errors.