Integrating Xilinx IP into FPGA VIs (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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LabVIEW uses the IP Integration Node to conveniently incorporate Xilinx IP into an FPGA VI. Complete the following steps to add Xilinx IP to an FPGA VI.

  1. Create a new, blank VI under a supported FPGA target and display the block diagram of the VI.
  2. Right-click the block diagram to select the Programming»Xilinx IP palette.
    Note  This palette displays only IP that your FPGA device family supports. Not all FPGA device families support all IP. Refer to the data sheet of an IP for information about FPGA family support.
  3. Find the IP you want and place it on the block diagram. LabVIEW creates a node to represent the IP.
  4. Double-click the node to launch its configuration dialog box.
    1. Enter an IP Name. LabVIEW displays this name on the block diagram icon.
    2. Specify a Folder for Support Files. This folder is the location where the Xilinx IP generator places necessary files. If you move the FPGA VI to another computer, you must move this folder also.
    3. Click Configure Xilinx IP to launch the Xilinx IP generator.
    4. Configure the IP as necessary. Use the < Back and Next > buttons to navigate through different options. You can click Datasheet or select the Documentation option, depending on your specific FPGA target, to view a PDF with detailed information about the IP.
    5. After you configure the IP, click Generate or OK, depending on your specific FPGA target. The Xilinx IP generator begins generating the VHDL code and returns you to LabVIEW. After the VHDL process finishes, the progress bar displays Generated IP successfully.
  5. Click Next to proceed through the rest of the configuration pages. Click Finish to finish configuring the Xilinx IP.


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