Debugging FPGA VIs Using Simulation Mode (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by executing the FPGA VI in simulation mode using simulated I/O. When you use this test method, LabVIEW generates random data for the inputs or uses a custom VI that you create to provide I/O. You also can use the FPGA Desktop Execution Node to communicate with FPGA resources that you select and to debug your FPGA design. For some FPGA targets, you also can execute the FPGA VI in simulation mode using real I/O.

When you run the FPGA VI in simulation on the development computer, you can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping, as well as debugging techniques that are specific to the FPGA host VI context.

Tip Tip  NI recommends that you debug and verify your FPGA design in software before compiling to avoid unnecessary compiles.

To debug your FPGA design in simulation mode using simulated I/O, select from the following options:

  • Sampling probes—Use this option to check intermediate values on a wire as a VI runs and to view changes in signal data over time.
  • FPGA Desktop Execution Node—Use this option if you need to test individual design elements of your FPGA VI, or for system-level testing for designs that rely on supported features. Supported features include front panel controls and indicators, I/O resources, and resources that use simulated time. Refer to the "Understanding Simulated Time on the Host" section for a list of features that use simulated time.
  • Custom VI test bench—Use this option if you need to create the data coming from a particular input or monitor an output.

Related Information

Compiling, Downloading, and Running FPGA VIs

Debugging Techniques

Sampling Probes

Use Sampling probes in host VIs or FPGA VIs to check intermediate values on a wire as a VI runs and to view changes in signal data over time, such as when you need to debug signals from a single-cycle Timed Loop. When you use a Sampling probe in a host VI, you must first specify a sampling source for the probe.

You cannot use the Sampling Probe Watch Window to change data. The probe has no effect on the way a VI runs.

Related Information

Using Sampling Probes

FPGA Desktop Execution Node

Before debugging an FPGA VI using a test bench, you can test the logic of the VI without compiling it by running the FPGA VI in simulation mode using simulated I/O. This test method saves compilation time, makes tests easier to repeat, and decreases the number of modifications necessary to create a test bench for additional debugging.

The FPGA Desktop Execution Node runs an FPGA VI in simulation mode using simulated I/O for a specified number of clock ticks. Use the FPGA Desktop Execution Node to test an individual loop containing IP you develop or an entire FPGA application with multiple loops running in parallel at different clock rates. Use this node to communicate with FPGA resources that you select and to debug your FPGA design.

Note Note  If you want to simulate your code continuously, you must place your LabVIEW FPGA code inside a While Loop.

Related Information

FPGA Desktop Execution Node

Debugging with the FPGA Desktop Execution Node

Testing and Debugging LabVIEW FPGA Code

Using the LabVIEW FPGA Desktop Execution Node

Custom VI Test Bench

You can create a custom VI to simulate I/O in LabVIEW for use as a test bench for your FPGA VI. You can use a custom VI as a test bench to create the data coming from a particular input or monitor an output. Every time an FPGA VI reads an input by calling an FPGA I/O Node, LabVIEW uses the custom VI you specify to provide the data. Using custom VIs for FPGA I/O creates a repeatable scenario for testing and makes it possible to change the data for a particular input. You also can use custom VIs for FPGA I/O to monitor an output from FPGA I/O Nodes.

(Statechart) You also can debug statecharts for an FPGA target on the development computer.

Related Information

Creating a Custom VI to Simulate I/O

Understanding Simulated Time

If you use certain FPGA resources and you execute the FPGA VI in simulation mode using simulated I/O, the resource uses simulated time instead of real time. Simulated time might be faster than real time depending on the number of events that occur during the simulation. For example, if you add a Wait (Simulated Time) VI to the block diagram and set the delay to 1000 ms, LabVIEW does not attempt to delay one second of real time. Instead, LabVIEW delays as long as necessary before executing the next scheduled action in the simulation.

The following resources use simulated time on the host:

  • While Loops
  • Single-Cycle Timed Loops
  • Wait (Simulated Time) VI
  • Loop Timer Express VI
  • Tick Count Express VI
  • FIFOs, except DMA FIFOs
  • Wait on Occurrence with Timeout in Ticks Function
  • Interrupt VI, when Wait Until Cleared is TRUE

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