Debugging with the FPGA Desktop Execution Node (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Use the FPGA Desktop Execution Node to test an individual loop containing IP you develop or an entire FPGA application with multiple loops running in parallel at different clock rates. Because the FPGA Desktop Execution Node executes an FPGA VI in simulation mode, you can develop tests for FPGA VIs that contain target resources, such as I/O and memory items.

Note Note  If you want to simulate your code continuously, you must place your LabVIEW FPGA code inside a While Loop.

Complete the following steps to debug an FPGA VI using the FPGA Desktop Execution Node:

  1. In the Project Explorer window, right-click the FPGA target and select Properties to display the FPGA Target Properties dialog box.
    Note Note  You also can right-click the FPGA target and select Select Execution Mode»Simulation (Simulated I/O).
  2. On the Execution Mode page, select Simulation.
  3. From the pull-down menu, select Use Simulated I/O.
  4. From the host VI, add the FPGA Desktop Execution Node to the block diagram.

  5. Configure the FPGA Desktop Execution Node. LabVIEW creates block diagram inputs or outputs for the FPGA resources you specify. Select the resources that you want to debug.
  6. Click OK to finish configuring the FPGA Desktop Execution Node.
  7. Run the host VI. You now can use standard LabVIEW debugging tools to analyze the simulated data the FPGA Desktop Execution Node returns.

Related Information

FPGA Desktop Execution Node

Testing and Debugging LabVIEW FPGA Code

Using the LabVIEW FPGA Desktop Execution Node

Debugging FPGA VIs Using Simulation Mode

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