Using Sampling Probes (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Use Sampling probes in host VIs or FPGA VIs to check intermediate values on a wire as a VI runs and to view changes in signal data over time. For example, you can use Sampling probes to debug VIs in a single-cycle Timed Loop or in code that is intended for a single-cycle Timed Loop. With Sampling probes, you can visualize multiple signals on a waveform graph and compare how the value of each signal changes cycle by cycle.

Note Note  Sampling probes support only scalar, non-cluster data types, such as fixed-point numbers, Booleans, and integers.

To view data from Sampling probes, use the Sampling Probe Watch Window. You cannot use the Sampling Probe Watch Window to change data. Sampling probes have no effect on the way a VI runs.

Understanding Sampling Sources

A sampling source determines when LabVIEW reads or samples data from associated probes. The sampling source ensures that Sampling probes update at the correct times relative to other Sampling probes associated with that source. There is no limit on the number of sampling sources you can specify. All probes associated with a given sampling source display on the same waveform graph in the Sampling Probe Watch Window.

The following table indicates some of the differences between sampling sources in the host VI and the FPGA VI:

TargetAvailable Sampling SourcesAutomatically Created?Sampling Behavior
HostFor Loops and While LoopsNo. You must first specify a sampling source before you use the Sampling probe in a host VI. LabVIEW reports probe data when the sampling source loop finishes executing an iteration.
FPGAFPGA simulated time
Note Note  In the FPGA VI, LabVIEW supports using Sampling probes only in single-cycle Timed Loops. Probes placed outside a single-cycle Timed Loop might not be accurate with respect to timing.
YesLabVIEW reports probe data on each rising edge of the clock associated with the single-cycle Timed Loop containing the probe.
Note Note  Because LabVIEW reports probe values when a loop designated as a sampling source completes execution, it is possible for a given probe to return multiple values in one iteration. For example, a probe might have multiple values in one iteration if the probe is in a For Loop or subVI that LabVIEW calls multiple times. The Sampling Probe Watch Window displays only the most recent data from the probe.

Specifying a Sampling Source in a Host VI

Complete the following steps to designate a loop as a sampling source on the block diagram of a host VI:

  1. Add either of the following loops to the block diagram.

    For Loop

    While Loop

  2. Right-click the loop border and select Mark as Probe Sampling Source to create the sampling source and display the Sampling Probe Watch Window.

    LabVIEW automatically lists and numbers the sampling source in the Sampling Probe Watch Window and displays the same number in a glyph in the top left corner of the loop.

Specifying a Sampling Source in an FPGA VI

LabVIEW automatically creates the FPGA sampling source using FPGA simulated time when you create the first Sampling probe. This sampling source is not tied to any individual structure on the block diagram, but you must use it within a single-cycle Timed Loop.

Creating a Sampling Probe on the Block Diagram

Complete the following steps to add a Sampling probe to the block diagram:

  1. Right-click a wire and select Sampling Probe»x, where x is the name of the sampling source.

    (FPGA VI) The Sampling Probe Watch Window appears.

    (Host VI) The Sampling Probe Watch Window is already open.

    LabVIEW automatically lists and numbers the probe in the Sampling Probe Watch Window and displays the same number in a glyph on the wire you clicked.
  2. (Optional) Place more probes on other wires and objects in the VI where you expect the data to change. Move the Sampling Probe Watch Window out of the way if necessary.
  3. Run the VI. The waveform graph on the right side of the Sampling Probe Watch Window displays data passed along the wire.
  4. (Optional) To locate the probed wire in the Sampling Probe Watch Window, right-click the wire associated with the probe and select Find Probe from the shortcut menu. The view in the Sampling Probe Watch Window snaps to the selected probe.
  5. Compare the data that appears in the Sampling Probe Watch Window to what you expect.
  6. To remove a sampling probe, select the sampling probe in the Sampling Probe Watch Window and click Remove Selected Probe on the Sampling Probe Watch Window toolbar. Click Remove all to remove the currently displayed sampling source and all associated probes.

    All probes close automatically when you close the Sampling Probe Watch Window or the block diagram.

Related Information

Sampling Probe Watch Window

Customizing Graphs and Charts

Debugging FPGA VIs Using Simulation

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