|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Owning Palette: FPGA Interface VIs and Functions
Requires: FPGA Interface
Executes an FPGA VI in simulation mode with simulated I/O for the specified number of clock ticks. This node writes all inputs, passes the amount of simulated time you specify, then reads all outputs. The FPGA VI pauses execution until LabVIEW calls the FPGA Desktop Execution Node again, at which point the FPGA VI resumes for the specified number of clock ticks.
|Dialog Box Options|
|Block Diagram Inputs|
|Block Diagram Outputs|
|Simulation Configuration||Contains the following options:|
|Terminal Configuration||Contains the following options:|
|Error In||Describes error conditions that occur before this node runs.|
|Error Out||Contains error information. This output provides standard error out functionality.|
You must set the execution mode of the target to Simulation (Simulated I/O). You cannot use this node with a custom VI for FPGA I/O. You cannot use this node with the User-Controlled I/O Sampling functions.
If you want to simulate your code continuously, you must place your LabVIEW FPGA code inside a While Loop.
Refer to the following VIs for examples of using the FPGA Desktop Execution Node Express VI: