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More Options for Multistage Multirate FIR Filter Dialog Box

LabVIEW 2013 Digital Filter Design Toolkit Help

Edition Date: June 2013

Part Number: 371988F-01

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Requires: Digital Filter Design Toolkit

Right-click an FPGA target in the Project Explorer window and select Start IP Generator from the shortcut menu to display the Start IP Generator dialog box. Select Multistage Multirate Filter and click the OK button to display the Generate LabVIEW FPGA Code for Multistage Multirate Filter dialog box. Load a finite impulse response (FIR) filter and click the More Options button to display the More Options for Multistage Multiate FIR Filter dialog box.

Note  The Start IP Generator dialog box is available only if you install the LabVIEW FPGA Module and NI-RIO driver software on the host computer.

Use the More Options for Multistage Multirate FIR Filter dialog box to configure additional settings to generate LabVIEW FPGA code for multistage multirate fixed-point filters. You can implement the resulting LabVIEW FPGA code on NI FPGA targets to perform fixed-point filtering.

This dialog box includes the following tabs and components:

  • General—Contains the following options:
    • Multiply Configuration—Configures the multiply according to different FPGA clock requirements.
      • Number of pipelining stages—Specifies the number of pipelining stages in the multiply. The more pipelining stages in the multiply, the higher FPGA clock rate at which the multiply can compile. The value must be an integer in the range [0, 4]. The default is 1.
      • Register inputs—Specifies whether to add a register to the multiply immediately after the multiplicand input and the coefficient input. The multiply can compile at a higher FPGA clock rate if these inputs are from block memory.
    • Memory Types—Specifies to store data in either the FPGA block memory or look-up tables.
      • State memory—Specifies the type of memory to store internal states. You can choose from the following options:
        • Automatic (default)
        • Block Memory—Stores the data using embedded blocks of memory.
        • Look-Up Table—Stores the data in look-up tables available on the FPGA.
      • Coefficient memory—Specifies the type of memory to store filter coefficients. You can choose from the following options:
        • Automatic (default)
        • Block Memory—Stores the data using embedded blocks of memory.
        • Look-Up Table—Stores the data in look-up tables available on the FPGA.
    • Number of Adder Levels per Register—Specifies the number of adder levels per register. Use a smaller value for higher FPGA clock rates at which you want to compile. The default is 2. You can choose from the following options:
      • 1 (maximum 2 inputs)
      • 2 (maximum 4 inputs)
      • 3 (maximum 8 inputs)
    • Number of parallel data paths—Specifies the number of parallel data paths in the generated FPGA filter. Different data paths share the same control logic and coefficient memory to increase resource efficiency. The LabVIEW Digital Filter Design Toolkit uses one parallel data path for multistage multirate FIR filters.
    • Execution Mode—Specifies whether to generate a filter block to execute outside or inside a single-cycle Timed Loop (SCTL). For the same multistage multirate FIR filter, the two execution modes have the same throughput performance. The Digital Filter Design Toolkit generates a filter block outside an SCTL for multistage multirate FIR filters.

 

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