LabVIEW 2013 Digital Filter Design Toolkit Help
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Requires: Digital Filter Design Toolkit
Right-click an FPGA target in the Project Explorer window and select Start IP Generator from the shortcut menu to display the Start IP Generator dialog box. Select Single-Rate Filter or Multirate Filter and click the OK button to display the Generate LabVIEW FPGA Code for Single-Rate Filter dialog box or Generate LabVIEW FPGA Code for Multirate Filter dialog box. Load a finite impulse response (FIR) filter and click the Throughput configuration button to display the Throughput Configuration dialog box.
|Note The Start IP Generator dialog box is available only if you install the LabVIEW FPGA Module and NI-RIO driver software on the host computer.|
Use the Throughput Configuration dialog box to configure additional throughput settings to generate LabVIEW FPGA code for single-rate or multirate fixed-point filters. You can implement the resulting LabVIEW FPGA code on NI FPGA targets to perform fixed-point filtering.
This dialog box includes the following options:
- Specifications—Specifies the settings for implementing the filter.
- Total number of channels—Specifies the total number of channels you want this filter to process.
- Input sampling frequency—Specifies the expected input sampling frequency of each channel.
- FPGA clock rate—Specifies the FPGA clock rate at which the filter runs. You can specify the value according to the application requirements. The default is 40 MHz, which is the same as the default LabVIEW FPGA clock rate. A higher FPGA clock rate means you can compile at a higher input sampling frequency or a larger number of channels.
- Optimization—Specifies the criteria for choosing the recommended configuration to use to implement this filter. You can choose from the following options:
- Minimum number of parallel data paths—Choose this option if you have sequential interleaved multiple channel inputs.
- Minimum number of MACs—Choose this option if you have parallel multiple channel inputs or the built-in multiply on the FPGA is a critical resource.
- Execution Mode—Specifies whether to generate a filter block to execute outside or inside a single-cycle Timed Loop (SCTL). For the same single-rate FIR filter, the two execution modes have a different throughput performance. This option is available only for a single-rate FIR filter as it does not affect the throughput performance for a multirate FIR filter. You can choose from the following options:
- Outside single-cycle Timed Loop—Specifies a generated filter block to execute outside an SCTL.
- Inside single-cycle Timed Loop—Specifies a generated filter block to execute inside an SCTL.
|Note Filters that run inside an SCTL use handshaking terminals.|
- Recommended Configuration—Indicates the recommended configuration to use to implement this filter.
- Number of parallel data paths—Indicates the recommended number of parallel data paths in the generated FPGA filter.
- Number of channels—Indicates the number of channels to process for each data path in the generated FPGA filter. The product of Number of channels and Number of parallel data paths is greater than or equal to Total number of channels. You can specify Number of channels in the Generate LabVIEW FPGA Code for Single-Rate Filter dialog box or the Generate LabVIEW FPGA Code for Multirate Filter dialog box.
|Note If the product of Number of channels and Number of parallel data paths is greater than Total number of channels, you must append zeros to the data sources to mimic the situation where Total number of channels is equal to the product of Number of channels and Number of parallel data paths.|
- Throughput—Indicates the minimum number of cycles between two successive values of valid input data in each data path. You can specify Throughput in the Generate LabVIEW FPGA Code for Single-Rate Filter dialog box or the Generate LabVIEW FPGA Code for Multirate Filter dialog box.
- Results—Indicates the performance of the generated FPGA filter based on the recommended configuration and specifications.
- Expected input throughput—Indicates the input throughput calculated from the filter specifications, in cycles/sample. Expected input throughput is FPGA clock rate/(Input sampling frequency*Total number of channels).
- Achieved input throughput—Indicates the actual input throughput you can achieve from the recommended configuration, in cycles/sample. Achieved input throughput is (Throughput/Number of parallel data paths). If Achieved input throughput is less than or equal to Expected input throughput, the generated FPGA filter can achieve the specifications.
|Note If the generated FPGA filter can not achieve the expected throughput specifications, you receive a warning.|
- Total number of MACs—Indicates the total number of multiply-accumulate units used in the generated FPGA filter, for all data paths.