**Requires:** Digital Filter Design Toolkit

Right-click an FPGA target in the Project Explorer window and select **Start IP Generator** from the shortcut menu to display the **Start IP Generator** dialog box. Select **Single-Rate Filter** and click the **OK** button to display the **Generate LabVIEW FPGA Code for Single-Rate Filter** dialog box.

Note The Start IP Generator dialog box is available only if you install the LabVIEW FPGA Module and NI-RIO driver software on the host computer. |

Use the **Generate LabVIEW FPGA Code for Single-Rate Filter** dialog box to generate LabVIEW FPGA code for fixed-point single-rate filters. You can implement the resulting LabVIEW FPGA code on NI FPGA targets to perform fixed-point filtering.

This dialog box includes the following options:

**Files**—Contains the following options:**Filter file to load**—Specifies the filter file from which you want to generate LabVIEW FPGA code. You can obtain the filter file by using the DFD Save to File VI.**Note**If you did not quantize the filter, LabVIEW quantizes it by using the default settings of the DFD FXP Quantize Coef VI.**Filter VI to generate**—Specifies the full path to the filter VI that LabVIEW generates, including the filename.

**Fixed-Point Modeling**—Specifies the settings for modeling the filter. If you already modeled the filter, LabVIEW loads the modeling settings from the filter file. You can choose from the following options:**Input Data Type**—Specifies the input word length and input integer word length of the filter.**Word length**—Specifies the word length, in number of bits, that LabVIEW uses to represent the input signal. The valid range is [1, 32].**Integer word length**—Specifies the integer word length, in number of bits, that LabVIEW uses to represent the input signal. The valid range is [–2048, 2047].

**Output Data Type**—Specifies the output word length and output integer word length of the filter.**Adapt to source**—Specifies whether LabVIEW decides the word length and integer word length of the output signal.**Word length**—Specifies the word length, in number of bits, that LabVIEW uses to represent the output signal. The valid range is [1, 32].**Integer word length**—Specifies the integer word length, in number of bits, that LabVIEW uses to represent the output signal. The valid range is [–2048, 2047].

**Rounding mode**—Specifies the rounding mode that LabVIEW uses in the output quantizer.**Overflow mode**—Specifies how LabVIEW handles overflows and underflows in the output quantizer.

**Magnitude Responses**—Displays the plot of the magnitude responses of the reference floating-point filter and the fixed-point filter.**Implementation**—Specifies the settings for implementing the filter. You can choose from the following options:**Number of channels**—Specifies the number of channels that you want the generated code to process for each data path. If you use the**Multiply-Accumulate**method to implement the filter, the valid range is [1, 255]. If you use the**Distributed Arithmetic**method to implement the filter, the valid range is [1, 8]. The default is 1.**Note**The generated single-rate filter block has one input and one output. For a multi-channel single-rate filter, data from multiple channels is interleaved into a single input. You are responsible for controlling the data sequence into/out of the filter block.**Throughput**—Specifies the minimum number of cycles between two successive values of valid input data.**Throughput configuration**—Displays the Throughput Configuration dialog box.**Method**—Specifies the method of implementing the filter. The**Multiply-Accumulate**method uses multipliers and accumulators to implement the filter, whereas the**Distributed Arithmetic**method uses look-up tables and accumulators. You can select the**Distributed Arithmetic**method for only single-rate FIR filters.**Tip**You can use the**Distributed Arithmetic**method to implement a high-throughput filter. However, this method might consume more FPGA logic resources than the**Multiply-Accumulate**method.**Note**If you use the**Distributed Arithmetic**method, the numeric precision of the filtering result might be slightly different from that of the simulation result.

**Feedback**—Displays information about the filter type and LabVIEW FPGA code generation, such as the maximum input sampling frequency per channel.**More Options**—Configures additional settings for generating the LabVIEW FPGA code. Click this button to display the More Options for Single-Rate FIR Filter dialog box.