PXIe-5668 Timing Configurations

NI RF Vector Signal Analyzers (NI-RFSA 18.1) Help

Edition Date: June 2018

Part Number: 372058U-01

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The timebases of the PXIe-5624 IF digitizer and the PXIe-5653 synthesizer/LO source module must be frequency-locked to a common reference clock. The following clock sources are available:

  • 4 GHz PXIe-5653 synthesizer/LO source LO2 signal—The 4 GHz (LO2) signal from the PXIe-5653 is used for both the PXIe-5606 and the PXIe-5624. The 4 GHz signal is used as a clock reference for the ADC inside the PXIe-5624.
  • 100 MHz PXIe-5653 LO synthesizer/LO source onboard Reference Clock—The PXIe-5653 supplies this 100 MHz source through the REF OUT (100 MHz) connector.
  • 10 MHz external Reference Clock—Connect the external clock signal, from your stable frequency reference, to the REF IN connector on the PXIe-5653.
  • 10 MHz PXI backplane clock—This 10 MHz Reference Clock signal is supplied on the PXI backplane.
Note Note   Although using the 10 MHz PXI backplane clock as a a reference is possible, NI does not recommend doing so. The frequency accuracy and stability of the 10 MHz PXI backplane reference results in increased phase noise.
Note Note  Do not use the PXIe-5653 REF OUT (10 MHz) connector as a reference source for timing configurations.

Onboard Reference Clock Timing Configuration

The default configuration of the PXIe-5668 allows the PXIe-5653 to export a 4 GHz LO2 signal to the PXIe-5624 so that the PXIe-5624 and the PXIe-5653 devices are frequency-locked.

The default cable configuration for the PXIe-5668 is shown in the following figure.

5668 VSA Interconnected

To configure the PXIe-5668 to use the PXIe-5653 internal clock, complete the following steps:

  1. Connect the LO2 OUT connector on the PXIe-5606 front panel to the CLK IN connector on the PXIe-5624 IF digitizer front panel.
  2. Set the Ref Clock Source property to OnboardClock or the NIRFSA_ATTR_REF_CLOCK_SOURCE attribute to NIRFSA_VAL_ONBOARD_CLOCK_STR.

External Reference Clock Timing Configuration

You can also configure the PXIe-5668 to lock to an external reference source by specifying REF IN as the Reference Clock source with the niRFSA Configure Ref Clock VI or the niRFSA_ConfigureRefClock function.

When configuring an external clock, you also need to set the Reference Clock rate if you do not want to use the default value of 10 MHz. The PXIe-5653 accepts any frequency from 5 MHz to 100 MHz in 1 MHz steps on the REF IN terminal as the Reference Clock. You can specify the desired clock rate with the niRFSA Configure Ref Clock VI or the niRFSA_ConfigureRefClock function.

PXI 10 MHz Backplane Clock Timing Configuration

In PXI Express RF vector signal analyzer configurations, NI recommends that you configure your system so that the PXIe-5624 digitizer uses the source provided by the PXIe-5606 LO2 OUT front panel connector; however, you can also configure the PXIe-5668 to lock to the PXI 10 MHz backplane clock. Doing so results in worse phase noise.

To configure the PXIe-5668 to use the PXI 10 MHz backplane clock, set the Ref Clock Source property to PXI_Clk or the NIRFSA_ATTR_REF_CLOCK_SOURCE attribute to NIRFSA_VAL_PXI_CLK_STR. The PXIe-5653 can lock to the PXI Express backplane Reference Clocks if the backplane Reference Clocks meet the frequency accuracy requirements of the PXIe-5653.

Note Note  The PXI Express backplane Reference Clock, when left free running, may not meet the accuracy requirements of the PXIe-5653. The PXIe-5653 requirements are more stringent than PXI Express backplane accuracy requirements because of the high-performance OCXO on the PXIe-5653. Thus locking to the PXI Express backplane Reference Clock requires that the PXI Express backplane Reference Clock be locked to another, more accurate external reference.

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