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Generating LabVIEW FPGA Code (Adaptive Filter Toolkit)

LabVIEW 2013 Adaptive Filter Toolkit Help

Edition Date: June 2013

Part Number: 372357B-01

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After you simulate a fixed-point adaptive filter, you can generate LabVIEW FPGA code for that fixed-point adaptive filter.

Note  You can generate LabVIEW FPGA code for fixed-point adaptive filters that use only the standard least mean squares (LMS) algorithm. To generate LabVIEW FPGA code for a fixed-point adaptive filter, you must install the LabVIEW FPGA Module on the host computer. You can deploy LabVIEW FPGA code only to National Instruments FPGA targets.

Each FPGA target has a limited amount of available computational resources, such as multipliers and memory units. The LabVIEW FPGA code you generate for a fixed-point adaptive filter also has a maximum input sampling frequency that the FPGA target can process. You must consider both computational resources and the sampling frequency when implementing a fixed-point adaptive filter on an FPGA target.

Estimating the FPGA Resource Requirements

Adaptive filters involve multiplication and addition operations. These multiplication operations require multipliers on FPGA targets. Depending on the word length of the input signals and filter coefficients, adaptive filters require different amounts of multipliers. The following table lists the number of built-in 18x18 multipliers that an adaptive filter with the standard least mean squares (LMS) algorithm requires.

Word Length of Input Signal x(n) Word Length of Input Signal d(n) Word Length of Filter Coefficients w(n) Required Number of Built-In Multipliers
16 16 16 3
16 16 24 4
16 >16 16 5
16 >16 24 6
>16 16 16 5
>16 16 24 7
>16 >16 16 8
>16 >16 24 10

Adaptive filters also require memory units on the FPGA target to store filter coefficients. When you increase the filter length, word length of the input signals, or word length of the filter coefficients, you must provide more and larger memory units for an adaptive filter. If you place a checkmark in the Read coefficients? checkbox of the Generate LabVIEW FPGA Code for LMS Adaptive Filter dialog box, the adaptive filter requires one additional memory unit.

Note  Different FPGA targets provide different numbers and sizes of memory units. Refer to the FPGA target documentation for information about the number and size of available memory units.

Estimating the Maximum Input Sampling Frequency

In addition to estimating the necessary computational resources, you also must estimate the maximum input sampling frequency fs that an FPGA target can process. The LabVIEW Adaptive Filter Toolkit calculates fs by using the following equation:

fs = 40 MHz / (2n+13)

where (2n+13) is the number of ticks that the LabVIEW FPGA code requires to calculate one data sample, and n is the filter length. Notice that this maximum input sampling frequency is for an FPGA target with a clock rate of 40 MHz. One tick is one clock cycle, and the clock rate you specify when compiling the FPGA VI determines the length of the clock cycle. Execution time might vary because of the call overhead in loop structures.

If the sampling frequency of the input signal is greater than the maximum input sampling frequency of the LabVIEW FPGA code, you must reduce the filter length of the fixed-point adaptive filter, simulate the fixed-point adaptive filter with the new filter length, and generate LabVIEW FPGA code again.

Generating LabVIEW FPGA Code for a Fixed-Point Adaptive Filter

Complete the following steps to generate LabVIEW FPGA code for a fixed-point adaptive filter.

  1. Open or create a LabVIEW project that contains an FPGA target. If you create a new project file, you must save this project file before generating LabVIEW FPGA code for the fixed-point adaptive filter.

  2. Right-click the FPGA target in the Project Explorer window and select Start IP Generator from the shortcut menu. LabVIEW displays the Start IP Generator dialog box.
  3. Choose LMS Adaptive Filter in the Start IP Generator dialog box and click the OK button to display the Generate LabVIEW FPGA Code for LMS Adaptive Filter dialog box.
  4. In the Filter name text box, specify the fixed-point adaptive filter name that appears in the resulting LabVIEW FPGA code.
  5. (Optional) Place a checkmark in the Read coefficients? checkbox if you want to access the coefficients of the fixed-point adaptive filter.
  6. Click the Load FXP Settings button to load the fixed-point adaptive filter settings. You also can specify these settings manually.
  7. Click the OK button to start generating LabVIEW FPGA code. The Adaptive Filter Toolkit generates the LabVIEW FPGA code in the same directory as the project file.

The following figure shows an example project that contains LabVIEW FPGA code for a fixed-point adaptive filter.

In the previous figure, FXP LMS is the name you specified in the Filter name text box. The example project contains the following fixed-point adaptive filter items:

  • FXP LMS—This folder contains all the items related to the fixed-point adaptive filter from which you generated LabVIEW FPGA code.
  • FXP LMS Coefficients—This item is an FPGA memory unit that stores the coefficients of the fixed-point adaptive filter. This item appears only if you place a checkmark in the Read coefficients? checkbox of the Generate LabVIEW FPGA Code for LMS Adaptive Filter dialog box.
  • FXP LMS.vi—This VI is the primary VI of the generated LabVIEW FPGA code. To use the adaptive filter on an FPGA target, drag and drop this VI on the block diagram.
  • FXP LMS Coefficients Converter.vi—This VI converts the adaptive filter coefficients from integers to fixed-point representation. This VI appears only if you place a checkmark in the Read coefficients? checkbox of the Generate LabVIEW FPGA Code for LMS Adaptive Filter dialog box.

Resolving LabVIEW FPGA Code Compilation Failures

In certain situations, the LabVIEW FPGA code might not compile successfully. Compilation failures occur when the number or size of the built-in multipliers and memory units does not meet the requirements of the fixed-point adaptive filter. For example, the NI cRIO-9104 has 96 built-in 18x18 multipliers. If a particular adaptive filter requires 10 18x18 multipliers, you can run a maximum of nine adaptive filters on this FPGA target. These nine adaptive filters use a total of 90 multipliers. If you attempt to run a tenth adaptive filter, the number of required multipliers becomes 100, and code compilation fails. If you encounter compilation failures, try reducing the filter length or the word length of the filter coefficients and simulating the fixed-point adaptive filter again.


 

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