Each FlexRIO adapter module ships with socketed component-level (CLIP) items that determine the module I/O available for use in the LabVIEW project. Refer to the specific CLIP reference topic for your adapter module for a list of available socketed CLIP items and provided signals.
|Note In software, FlexRIO adapter modules are referred to as IO Modules.|
To add a socketed CLIP item to your LabVIEW project, complete the following steps:
The IO Module item in the Project Explorer window always displays the name of the currently configured adapter module and CLIP in the following format:
(<IO Module Name> : <Component Level IP Name>)
The following figure shows a properly configured adapter module in the LabVIEW Project Explorer window. The module number and available I/O signals that appear vary depending on the FlexRIO adapter module and CLIP option you use.
The FPGA I/O for the currently selected CLIP automatically populates beneath the IO Module item in the Project Explorer window. This I/O can be dragged from the Project Explorer and dropped directly onto a LabVIEW VI for configuration using the FPGA I/O nodes.
|Note The default configuration of FPGA I/O uses synchronization registers to avoid metastability problems with asynchronous signals. When FPGA I/O is designed to run synchronous to the clock domain from which it is accessed, these synchronization registers are unnecessary and may cause unwanted latency. To avoid latency resulting from this configuration, set the number of synchronization registers to 0 for synchronous interfaces. Refer to the Advanced Code Generation FPGA I/O Properties Page for more information about configuring synchronization registers.|