IO Module Details Properties Page

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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In the IO Module Properties dialog box, select Details from the Category list to display this page.

Use this page to view detailed information about the adapter module that is currently selected in the IO Module General Properties page. This information is populated in the LabVIEW project from the associated adapter module configuration file (.fam).

Adapter Module Configuration (.fam) Values

The following sections contain detailed descriptions of each of the supported configuration values contained with the .fam file.

  • Manufacturer—Specifies the manufacturer of the currently configured adapter module.
  • Model—Specifies the model name of the configured adapter module. This name displays in the LabVIEW project with the adapter module.
  • VccoA/VccoB—Specifies the voltage level that the VccoA and VccoB banks, respectively, are configured to use when you download an application compiled for use with the adapter module to the FPGA. Use this component with the NI PXI-795xR and NI PXIe-796xR devices only.
  • Vcco—Specifies the voltage level that the Vcco bank is configured to use when you download an adapter module application to the FPGA. Use this component with the NI PXIe-797xR devices only.
  • IOModuleID—If the selected adapter module has an EEPROM, this indicator displays the stored 32-bit IO Module ID. If the selected adapter module does not have an EEPROM, this indicator displays <No EEPROM>.
  • Default Component Level IP—Specifies the declaration name of the component-level IP (CLIP). This CLIP is automatically configured for use when you create a new LabVIEW project and MAX recognizes the FlexRIO device and the attached adapter module.
  • GPIO Constraints—Specifies the FPGA pin constraint that the FPGA compilation uses for this adapter module. The Constraints section of the adapter module configuration (.fam) file defines this information. Use the Constraints section to constrain the I/O Standard for each FPGA pin that is used by a GPIO line to the adapter module connector. These constaints should match the I/O Standard that the adapter module is designed to use.
  • Sync Clock—Configures the IoModSyncClk signal supplied to the adapter module. The default setting for Sync Clock is the value specified in the adapter module configuration (.fam) file.
    Note Note  You must recompile the VI after changing the Sync Clock value.
  • Power Rail Sequence—Specifies the power-up sequence that the power rails use when you download an adapter module application to the FPGA.
    Note Note  Use this component with the NI PXIe-797xR devices only.
  • IO Module Configuration File Path—Specifies the path to the adapter module configuration file (.fam) for the currently selected adapter module.

For more information about the .fam file, refer to the FlexRIO Adapter Module Development Kit User Manual.

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