NI 5734 CLIP

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides access to four analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:

  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the CLK IN connector
  • External Sample Clock through the CLK IN connector
  • Internal Sample Clock locked to an external Reference Clock through Sync Clock

This CLIP also contains an engine to program the ADC and clock, either through predetermined settings for an easier instrument setup, or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 16-bit analog input data is accessed using a left-justified U16 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean indicators.

The NI 5734 allows you to configure the clock, gain, filter, coupling, and other settings in the NI LabVIEW FPGA Module software.

  • Use the User Command, User Data 0, and User Data 1 signals to configure these settings.
  • Use the User Command Commit signal to apply these settings.
  • Use the User Return signal to read configured settings.
  • Use the User Command Status signal to determine whether the previous command was expected successfully.
  • Use the User Error signal to determine if you must reinitialize the device due to an error.

Refer to the User Command Table for more information about values for these signals.

User Command Table

User Setting User Command Value (U8) User Data 0 Value (U8) User Data 1 Value (U8) User Return Value (U16)
Clock Settings 0 0 = Internal Sample Clock

1 = Internal Sample Clock locked to an external Reference Clock through the CLK IN connector

2 = External Sample Clock through the CLK IN connector

3 = Internal Sample Clock locked to an external Reference Clock through Sync Clock
N/A N/A
Filter Settings 1 0 = AI CH0
1 = AI CH1
2 = AI CH2
3 = AI CH3
0 = Bypasses filters
1 = Elliptic Filter
2 = Bessel Filter
N/A
Gain Settings 2 0 = AI CH0
1 = AI CH1
2 = AI CH2
3 = AI CH3
0 = 0 dB
1 = 6 dB
2 = 12 dB
N/A
Coupling Settings 3 0 = AI CH0
1 = AI CH1
2 = AI CH2
3 = AI CH3
0 = AC coupling
nonzero = DC coupling
N/A
Dither Enable 4 0 = AI CH0
1 = AI CH1
2 = AI CH2
3 = AI CH3
0 = Disabled
Nonzero = Enabled
N/A
Read Temperature 5 N/A N/A Temperature (0.0625 °C per LSB). The temperature sensor device returns a signed 12-bit number that is sign extended to be 16 bits. To scale the temperature value in °C, type cast the value to an I16 and multiply by 0.0625.
Read User EEPROM 6 EEPROM address to read data N/A Read data
Write User EEPROM 7 EEPROM address to write data Write data. N/A
Reinitialize 0xFF N/A N/A N/A
Note Note  To use the SPI address and data signals to program the NI 5734 ADC and clock chip, you must refer to the register map provided in each respective component datasheet. Refer to the NI 5731/5732/5733/5734R User Guide and Specifications document included with your device for the part numbers for the NI 5734 ADC and clock.

Example Projects

The FlexRIO driver installation includes the following example projects to help get you started with the NI 5734 CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example projects use the I/O signals exposed by the NI 5734 CLIP:

  • NI 5734 - Clock Select.lvproj—This example continuously acquires records of analog input data from the NI 5734. You can select an AI channel, trigger type, and record size.
  • NI 5734 - Getting Started.lvproj—This example demonstrates how to select the desired clock configuration for the NI 5734 adapter module. The example continuously acquires records of analog input data from the NI 5734 and allows you to select an AI channel, trigger type, and record size.

For more information about the NI 5734, refer to the NI 5731/5732/5733/5734R User Guide and Specifications document, available from the Start menu and at ni.com/manuals.

The following table describes the NI 5734 CLIP I/O signals.

CLIP Signal Name Data Type Control/Indicator Description
AI 0 U16 Indicator Analog input data through the AI 0 connector.
AI 0 Over Range Bool Indicator A TRUE value indicates that the input signal on the AI 0 connector is beyond the full-scale range.
AI 1 U16 Indicator Analog input data through the AI 1 connector.
AI 1 Over Range Bool Indicator A TRUE value indicates that the input signal on the AI 1 connector is beyond the full-scale range.
AI 2 U16 Indicator Analog input data through the AI 2 connector.
AI 2 Over Range Bool Indicator A TRUE value indicates that the input signal on the AI 2 connector is beyond the full-scale range.
AI 3 U16 Indicator Analog input data through the AI 3 connector.
AI 3 Over Range Bool Indicator A TRUE value indicates that the input signal on the AI 3 connector is beyond the full-scale range.
Initialization Done Bool Indicator A TRUE value indicates that the device is ready to use after the CLIP runs an initial default setup.
PLL Locked Bool Indicator A TRUE value indicates that the PLL is locked. This signal is valid only when using a Reference Clock, either through the CLK IN connector or through the Sync Clock. If you are not using a Reference Clock, this signal is FALSE.
DC Over Voltage U8 Indicator Bit 0 corresponds with CH0, bit 1 corresponds with CH1, bit 2 corresponds with CH2, and bit 3 corresponds with CH3. The top four bits of the U8 are unused.

0 = Either AC-coupled mode is selected, or the voltage in DC-coupled mode is within ±2 V.
1 = While in DC-coupled mode, the voltage peaked beyond ±2 V and caused the device to change automatically into AC-coupled mode.
User Command U8 Control Configures the clock, filter, gain, coupling, and other settings for your device. Use this signal with the User Data 0 and User Data 1 signals to select values for these settings. Then apply these settings by selecting the User Command Commit signal. Refer to the User Command Table for more information about values for this signal.
User Command Commit Bool Control A low-to-high transition applies the settings configured with the User Command signal.
User Command Idle Bool Indicator A TRUE value indicates that the device is able to accept more commands from the User Command signal.
User Data 0 U8 Control Use this signal in conjunction with the User Data 1 and User Command signals to configure your device. Refer to the User Command Table for more information about values for this signal.
User Data 1 U8 Control Use this signal in conjunction with the User Data 0 and User Command signals to configure your device. Refer to the User Command Table for more information about values for this signal.
User Command Status U8 Indicator Indicates whether the previous command was successful or unsuccessful.

0 = Successful
Nonzero = Unsuccessful
User Return U16 Indicator Returns data configured by the User Command signal.
User Error U8 Indicator Indicates that an error occurred and that you must reinitialize the device.
DIO Port 0 Rd Data1 U8 Indicator Reads digital data through the AUX I/O connector on DIO Port 0 channels <0..3>. Bit 0 corresponds with DIO Port 0 (0), bit 1 corresponds with DIO Port 0 (1), and so on. The top four bits of the U8 are unused.
DIO Port 0 Wr Data1 U8 Control Writes digital data through the AUX I/O connector on DIO Port 0 channels <0..3>. Bit 0 corresponds with DIO Port 0 (0), bit 1 corresponds with DIO Port 0 (1), and so on. The top four bits of the U8 are unused.
DIO Port 0 WE1 Bool Control Configures DIO Port 0 channels <0..3> on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
DIO Port 1 Rd Data1 U8 Indicator Reads digital data through the AUX I/O connector on DIO Port 1 channels <0..3>. Bit 0 corresponds with DIO Port 1 (0), bit 1 corresponds with DIO Port 1 (1), and so on. The top four bits of the U8 are unused.
DIO Port 1 Wr Data1 U8 Control Writes digital data through the AUX I/O connector on DIO Port 1 channels <0..3>. Bit 0 corresponds with DIO Port 1 (0), bit 1 corresponds with DIO Port 1 (1), and so on. The top four bits of the U8 are unused.
DIO Port 1 WE1 Bool Control Configures DIO Port 1 channels <0..3> on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 0 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 0.
PFI 0 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 0 if the PFI 0 WE signal is set to TRUE.
PFI 0 WE1 Bool Control Configures PFI 0 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 1 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 1.
PFI 1 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 1 if the PFI 1 WE signal is set to TRUE.
PFI 1 WE1 Bool Control Configures PFI 1 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 2 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 2.
PFI 2 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 2 if the PFI 2 WE signal is set to TRUE.
PFI 2 WE1 Bool Control Configures PFI 2 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 3 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 3.
PFI 3 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 3 if the PFI 3 WE signal is set to TRUE.
PFI 3 WE1 Bool Control Configures PFI 3 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
SPI Idle Bool Indicator Indicates when the SPI interface to either the clock chip or ADCs is being accessed. To use the SPI signals, you must wait for this signal to be TRUE.
SPI Device Select U8 Control Selects which SPI device to interact with. The NI 5734 has two dual-channel ADCs, each of which is controlled by a single write signal. The SPI devices have the following values:

0 = Channel 0 ADC and Channel 1 ADC

1 = Channel 2 ADC and Channel 3 ADC

2 = Clock chip

3 = Clock adjust DAC
SPI Address U16 Control Configures the SPI address to read and write data.
SPI Read Data U8 Indicator Configures the SPI data to read from a selected chip at a SPI address.
SPI Read Bool Control Executes the settings of the SPI Read Data signal when this signal is on a FALSE-to-TRUE transition.
SPI Write Data U16 Control Configures the SPI data to write to a selected chip at a SPI address.
SPI Write Bool Control Executes the settings of the SPI Write Data signal when this signal is on a FALSE-to-TRUE transition.
Clock 40 MHz Clock You must select a 40 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality. Access only the User Command signals in this clock domain.
Sample Clock Constant Clock The FPGA clock used to sample analog input data. One sample from each ADC channel is valid on every rising edge of this clock. You must add Sample Clock to your project using the FPGA Base Clock Properties dialog box. Access only the following signals in this clock domain: AI 0, AI 0 Over Range, AI 1, AI 1 Over Range, AI 2, AI 2 Over Range, AI 3, and AI 3 Over Range.

1 You can access all DIO and PFI signals in any clock domain, but you still must comply with the physical clock capabilities of your device.

NI 5734 CLIP Clocks

The following table describes the NI 5734 CLIP clock signals.

CLIP Signal Name Description
CLK40 You must select a 40 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality. Access only the User Command signals in this clock domain.
Sample Clock2 The FPGA clock used to sample analog input data. One sample from each ADC channel is valid on every rising edge of this clock. You must add Data Clock to your project using the FPGA Base Clock Properties dialog box. Access only the following signals in this clock domain: AI 0, AI 0 Over Range, AI 1, AI 1 Over Range, AI 2, AI 2 Over Range, AI 3, and AI 3 Over Range.

2 The Sample Clock signal is only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
14.1 and later 14.1 and later Sample Clock
14.0 and earlier 14.0 and earlier IO Module Clock 0 and IO Module Clock 1

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