NI 5731/5732/5733/5734 Component-Level IP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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The FlexRIO Adapter Module Support software comes with component-level IP (CLIP) options that provide access to the NI 5731/5732/5733/5734 physical I/O from within the LabVIEW FPGA environment.

In the IO Module Properties dialog box, select National Instruments: NI 573x (where x corresponds with the hardware version of the NI 573x you are using) from the IO Modules list in the General category. The Component Level IP window automatically displays the compatible items.

To use a CLIP item with your LabVIEW project, select the CLIP item in the Component Level IP window and select OK. The I/O defined by the selected CLIP automatically populates the IO Module item in the Project Explorer window.

The following NI-developed CLIP options are compatible with the NI 5731/5732/5733/5734 devices.

CLIP NameCLIP Description
NI 5731 CLIPThis CLIP provides access to two analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:
  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the CLK IN connector
  • External Sample Clock through the CLK IN connector
  • Internal Sample Clock locked to an external Reference Clock through Sync Clock

This CLIP also contains an engine to program the ADC and clock, either through predetermined settings for an easier instrument setup, or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 12-bit analog input data is accessed using a left justified U16 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean indicators.

NI 5732 CLIPThis CLIP provides access to two analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:
  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the CLK IN connector
  • External Sample Clock through the CLK IN connector
  • Internal Sample Clock locked to an external Reference Clock through Sync Clock

This CLIP also contains an engine to program the ADC and clock, either through predetermined settings for an easier instrument setup, or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 14-bit analog input data is accessed using a left justified U16 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean indicators.

NI 5733 CLIPThis CLIP provides access to two analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:
  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the CLK IN connector
  • External Sample Clock through the CLK IN connector
  • Internal Sample Clock locked to an external Reference Clock through Sync Clock

This CLIP also contains an engine to program the ADC and clock, either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 16-bit analog input data is accessed using a left justified U16 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean indicators.

NI 5734 CLIPThis CLIP provides access to four analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:
  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the CLK IN connector
  • External Sample Clock through the CLK IN connector
  • Internal Sample Clock locked to an external Reference Clock through Sync Clock

This CLIP also contains an engine to program the ADC and clock, either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 16-bit analog input data is accessed using a left justified U16 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean indicators.


/images/reference/en-XX/help/372614J-01/caution.gif Caution  You can create custom CLIP items for the NI 5731/5732/5733/5734 devices. If you choose to develop a custom CLIP item for your application, NI recommends using one of the provided NI 5731/5732/5733/5734 CLIP items as a template while referring to your device specifications to ensure that you maintain the proper electrical characteristics. Failure to adhere to the specified electrical requirements and signal directions may result in device damage. National Instruments is not liable for any damage resulting from such misuse.

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