NI 5751 Multidevice Synchronization CLIP

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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The NI 5751 Multidevice Synchronization CLIP provides access to 16 analog input channels, eight digital input lines, and eight digital output lines. This CLIP also contains a SPI interface to program the ADC registers. Use this CLIP for applications that require synchronization across multiple NI 5751 modules. For more details on multidevice synchronization, refer to KnowledgeBase 5AN9QBLY at ni.com/support.

In the 5751 Multidevice Synchronization CLIP, each Sample Clock cycle generates a sample from the analog input channels. DStarA is the only Sample Clock that is routed. This CLIP only supports external Sample Clock rates from 30 MHz to 50 MHz. Each 14-bit sample is output to LabVIEW as an I16 data type. The 14-bit data is left-justified and padded with two zeros in the LSBs. DStarA is required to be routed to the CLIP from LabVIEW FPGA. The data is clocked out of the CLIP on DStarA.

Example Projects

The FlexRIO driver installation includes a variety of example projects to help you get started with the NI 5751 CLIP items. To access these examples in NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. By default, the example projects use the I/O signals exposed by the NI 5751 CLIP items.

The following example projects are available for use with the NI 5751 CLIP items. These examples demonstrate how to get data from the input and output terminals on the adapter module, and demonstrate some of the features of the ADCs on the NI 5751 adapter module.

  • NI 5751 Configure ADC.lvproj—This example uses the SPI bus to configure the adapter module analog to digital converters (ADCs). The example acquires a finite number of samples using an internal clock and passes the data to the host VI through an Acquisition FIFO.
  • NI 5751 Finite Acquisition Multiple Channels.lvproj—This example acquires a finite number of samples from multiple channels using an internal clock and passes the data to the host VI through an Acquisition FIFO.
  • NI 5751 Finite Acquisition with External Clock.lvproj—This example acquires a finite number of samples using an external clock or internal clock, and passes the data to the host VI through an Acquisition FIFO.
  • NI 5751 Multi Record Digital Trigger.lvproj—This example acquires multiple records from a single channel using an internal clock and an external digital trigger. The host VI transfers data through the Acquisition FIFO.

I/O Signals

The following table describes the I/O signals for the NI 5751 Multidevice Synchronization CLIP.

Port Name Data Type Function/Description
AI A <0..7> I16 Data from each of the eight channels on ADC A. If you are using the NI 5751 CLIP, data is clocked out of the CLIP on IO Module Clock 0. If you are using the NI 5751 Multidevice Synchronization CLIP, data is clocked out of the CLIP on DStarA. After Initialization Done is asserted, the data is valid on every clock cycle.
AI B <8..15> I16Data from each of the eight channels on ADC B. If you are using the NI 5751 CLIP, data is clocked out of the CLIP on IO Module Clock 0. If you are using the NI 5751 Multidevice Synchronization CLIP, data is clocked out of the CLIP on DStarA. After Initialization Done is asserted, the data is valid on every clock cycle.
DI <0..7> Boolean Digital Input. Refer to the Digital Input Terminals section of the NI 5751R User Guide and Specifications for more information.
DO <0..7> Boolean Digital Output. Refer to the Digital Output Terminals section of the NI 5751R User Guide and Specifications for more information.
Digital Output Enable Boolean Enables the digital outputs.
Force Initialization Boolean Forces a CLIP initialization.1 If you are using an external clock and the clock frequency changes, you must assert this signal manually. ADC registers retain their values when Force Initialization is manually asserted. This signal should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard clock.
Initialization Done BooleanWhen Initialization Done is asserted, initialization1 of the CLIP has completed.
AdcErrorA Boolean When ADC Error A is asserted, the width of the sampling window from ADC A is less than its required value, which does not guarantee correct data sampling. This condition could be caused by a noisy clock source, a damaged ADC, or an incompatible FlexRIO FPGA module. ADC Error A is a sticky bit and is cleared upon reinitialization.1
AdcErrorB Boolean When ADC Error B is asserted, the width of the sampling window from ADC B is less than its required value, which does not guarantee correct data sampling. This condition could be caused by a noisy clock source, a damaged ADC, or an incompatible FlexRIO FPGA module. ADC Error B is a sticky bit and is cleared upon reinitialization.1
PLL Unlocked BooleanIndicates that the PLL has become unlocked since the board was initialized. When the PLL is unlocked, IO Mod Clock 0 is disabled. When set, PLL Unlocked is cleared upon reinitialization.1
SPI Idle2 Boolean Indicates the SPI engine is idle and ready for a SPI read or write transaction. This signal should be inside a single-cycle Timed Loop with the 40 MHz onboard clock configured as the clock source.
SPI Device Select2 U8 Selects which ADC the SPI port will communicate with. This signal should be inside a single-cycle Timed Loop with the 40 MHz onboard clock configured as the clock source.

SPI Device SelectADC target
0x00ADC A
0x01ADC B


SPI Address2 U8 The address of the register in the selected ADC. This signal should be inside a single-cycle Timed Loop with the 40 MHz onboard clock configured as the clock source.
SPI Write Data2 U16 Data to be written to the register in the selected ADC. This signal should be inside a single-cycle Timed Loop with the 40 MHz onboard clock configured as the clock source.
SPI Write2 Boolean Begin SPI write transaction. This signal should be inside a single-cycle Timed Loop with the 40 MHz onboard clock configured as the clock source.

1 For more information, refer to the Initialization section.

2 For more information, refer to the Accessing SPI Registers section.

Initialization

During initialization, the CLIP items perform the following tasks:

  • Reset a PLL in the CLIP that is used to receive data from the ADCs.
  • Reset the deserialization circuit.
  • Recalibrate the data delays for capturing the data using dynamic phase alignment.
  • Align the two ADC ICs to each other.
  • Clear ADC Error X.

Manual Initialization

The user FPGA code must manually start initialization when using DStarA or CLK IN, as the ADC Sample Clock and the frequency of the clock has changed since the last initialization.

To manually start initialization, the user FPGA code must assert Force Initialization.

Note Note  When initialization starts, the Initialization Done signal deasserts within 100 ns. Initialization Done does not assert again until initialization has completed. You can expect a delay of up to two seconds before Initialization Done asserts again, depending on your clock rate. If you read the Initialization Done indicator before it has had time to deassert (100 ns), you may get a false positive error.

Automatic Initialization

The CLIP performs initialization automatically in the following instances:

  • The FPGA IO is enabled to the NI 5751
  • The user FPGA code changes the Sample Clock Select signal

FPGA IO is enabled automatically when the CLIP is loaded into the FPGA. You can also programmatically enable and disable the FPGA IO from the host VI. When FPGA IO is enabled, the CLIP resets all ADC registers.

Caution Caution  Do not execute user FPGA code using IO Module Clock 0 until Initialization Done is True. While Initialization Done is False, the clocks are not stable.

If the user FPGA code changes the Sample Clock Select signal, the CLIP begins initialization automatically; you do not need to assert Force Initialization.

Note Note  When initialization starts, the Initialization Done signal deasserts within 100 ns. Initialization Done does not assert again until initialization has completed. You can expect a delay of up to two seconds before Initialization Done asserts again, depending on your clock rate. If you read the Initialization Done indicator before it has had time to deassert (100 ns), you may get a false positive error.

Accessing SPI Registers

The ADC register maps are included in the AD9252 datasheet. For more information and SPI functionality for the AD9252, refer to the following application note on Analog Devices' website: AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

SPI reads from the AD9252 are not supported on the NI 5751. The SPI access does not actually take effect until the software transfer bit (bit 0) of the device_update (offset 0xFF) register is written.

To access a register in an ADC, complete the following steps:

  1. Configure the following:
    • SPI Device Select with which ADC to access.
    • SPI Address with the register offset.
    • SPI Write Data with the write data.
  2. Set SPI Write for a write transaction.
  3. Poll for SPI Idle to be True.

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