NI 5771 CLIP

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides access to two analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:

  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the REF IN connector
  • External Sample Clock through the CLK IN connector
  • Internal Sample Clock locked to an external Reference Clock through IoModSyncClock

This CLIP also contains an engine to program the ADC and clock circuit, either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 8-bit analog input data is accessed using a U8 data type. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean indicators.

Although real-time sampling is the default sampling mode on the NI 5771, the NI 5771 CLIP also supports Time Interleaved Sampling (TIS) on one analog input channel at a time. TIS enables the device to use both channels on the ADC to sample the same waveform at different relative phases, which increases the real-time sample rate. The NI 5771 then interleaves the samples to create a waveform as if only one ADC channel were sampling the waveform at twice the Sample Clock rate. To configure the NI 5771 for TIS mode using this CLIP, refer to the User Command Table.

In TIS mode, the data is returned on both the AI 0 Data <N-7..N> and AI 1 Data <N-7..N> signals even though the device is only sampling the single analog input channel that you selected with the User Data 1 signal. The first sample of data is always AI 1 Data N–7, regardless of which channel you are sampling. The following figure demonstrates TIS on an NI 5771 device:

Tis mode help

Note Note  The ADC data sheet refers to TIS as dual-edge sampling (DES).

Example Projects

The FlexRIO driver installation includes the following example projects to help get you started with the NI 5771 CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example projects use the I/O signals exposed by the NI 5771 CLIP:

The NI 5771 allows you to configure the clock, ADC, sampling, and other settings using the NI LabVIEW FPGA Module software.

  • NI 5771 Clock Select.lvproj—This example demonstrates how to select the desired clock configuration for the NI 5771 adapter module. The example continuously acquires records of analog input data from the NI 5771 and allows you to select an AI channel, trigger type, and record size.
  • NI 5771 Getting Started.lvproj—This example continuously acquires records of analog input data from the NI 5771 and allows you to select an AI channel, trigger type, and record size.
  • NI 5771 TIS Mode Enabled.lvproj—This example demonstrates how to enable Time Interleaved Sampling with the NI 5771 to achieve a sampling rate of 3 GS/s. This example continuously acquires records of analog input data from the NI 5771 and allows you to select an AI channel, trigger type, and record size.


User Commands

  • Use the User Command, User Data 0, and User Data 1 signals to configure these settings.
  • Use the User Command Commit signal to apply these settings.
  • Use the User Return signal to read configured settings.
  • Use the User Command Status signal to determine whether the previous command was expected successfully.
  • Use the User Error signal to determine if you must reinitialize the device due to an error.

Refer to the User Command Table for more information about values for these signals.

User Command Table

User Setting User Command Value (U8) User Data 0 Value (U16) User Data 1 Value (U8) User Return Value (U8)
Clock Settings 0 0 = Internal Sample Clock

1 = Internal Sample Clock locked to an external Reference Clock through the CLK IN connector

2 = External Sample Clock through the CLK IN connector (disables the CLK OUT connector)

3 = Internal Sample Clock locked to an external Reference Clock through Sync Clock
N/A N/A
ADC Self-Calibration 1 N/A N/A N/A
ADC Full Scale Range 2 Gain Setting = 0x0000 to 0x01FF

0x0000 = 560 mV, Minimum
0x0100 = 700 mV, Nominal
0x01FF = 840 mV, Maximum

0 = AI 0
1 = AI 1
N/A
ADC Offset 3 Positive Offset = 0x0000 to 0x00FF
Negative Offset = 0x0100 to 0x01FF

(0.176 mV per LSB)
0 = AI 0
1 = AI 1
N/A
TIS Mode 4 0 = TIS mode disabled
1 = TIS mode enabled
0 = AI 0
1 = AI 1
N/A
Frequency Adjust DAC Value 5 DAC value = 0x0000 to 0xFFFF N/A N/A
Read User EEPROM 6 EEPROM address to read data. N/A Read data.
Write User EEPROM 7 EEPROM address to write data. Write data. N/A
Exported Sample Clock 8 0 = CLK OUT disabled
1 = CLK OUT enabled
Note:  If you set this signal to a nonzero value and your device is already configured to use the external Sample Clock through the CLK IN connector, the User Command Status signal returns a nonzero value indicating that the command was unsuccessful.
N/A N/A
Reinitialize 0xFF N/A N/A N/A
Note Note  To use the SPI address and data signals to program the NI 5771 ADC and clock circuit, you must refer to the register map provided in each respective component datasheet. Refer to the NI 5771R User Guide and Specifications document included with your device for the part numbers for the NI 5771 ADC and clock circuit.

The FlexRIO driver installation includes the following example projects to help get you started with the NI 5771 CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example projects use the I/O signals exposed by the NI 5771 CLIP:

  • NI 5771 - Getting Started.lvproj
  • NI 5771 - Clock Select.lvproj

For more information about the NI 5771, refer to the NI 5771R User Guide and Specifications document available at ni.com/manuals.

The following table describes the NI 5771 CLIP I/O signals.

CLIP Signal Name Data Type Control/Indicator Description
AI 0 Data N-7 U8 Indicator Returns analog input data through the AI 0 front panel connector. Each sample is a U8 data type. If AI 1 is configured for TIS mode, these signals return time-interleaved samples for AI 1.
AI 0 Data N-6
AI 0 Data N-5
AI 0 Data N-4
AI 0 Data N-3
AI 0 Data N-2
AI 0 Data N-1
AI 0 Data N
AI 1 Data N-7 U8 Indicator Returns analog input data through the AI 1 front panel connector. Each sample is a U8 data type. If AI 0 is configured for TIS mode, these signals return time-interleaved samples for AI 0.
AI 1 Data N-6
AI 1 Data N-5
AI 1 Data N-4
AI 1 Data N-3
AI 1 Data N-2
AI 1 Data N-1
AI 1 Data N
AI Over Range Bool Indicator A TRUE value indicates that the input signal on either the AI 0 or AI 1 front panel connectors is beyond the full-scale range. This signal is synchronous to the analog input data.
Initialization Done Bool Indicator A TRUE value indicates that the device is ready to use after the CLIP runs an initial default setup.
PLL Locked Bool Indicator A TRUE value indicates that the PLL is locked. This signal is valid only when using a Reference Clock, either through the CLK IN connector or through the Sync Clock. If you are not using a Reference Clock, this signal is FALSE.
PLL Locked asserts when the phase-locked loop circuit reports that the voltage-controlled oscillator (VCO) locks to the Reference Clock. Once PLL Locked asserts, you may have to wait up to 6 seconds before the phase of the VCO fully settles. If your application requires you to lock to the external Reference Clock or to the backplane Reference Clock, you must ensure that this settling time has elapsed before taking data.
Synchronous Trigger Input U8 Indicator Specifies, with a resolution of two clock cycles, the time that the FPGA received a trigger signal from the TRIG front panel connector in relation to the samples taken. Only the lower four bits of the U8 are used.

0 = The trigger occurred on either AI x Data N or AI x Data N-1
1 = The trigger occurred on either AI x Data N-2 or AI x Data N-3
2 = The trigger occurred on either AI x Data N-4 or AI x Data N-5
3 = The trigger occurred on either AI x Data N-6 or AI x Data N-7
Asynchronous Trigger Input Bool Indicator Specifies whether the FPGA received an unclocked trigger signal from the TRIG front panel connector.

TRUE = The FPGA has received a trigger signal
FALSE = The FPGA has not received a trigger signal
Trigger WE Bool Control Configures the TRIG front panel connector for either reading or writing a trigger signal.

TRUE = enables the Trigger Output signal
FALSE = enables the Asynchronous Trigger Input and the Synchronous Trigger Input signals
Trigger Output Bool Control Writes a trigger signal through the TRIG front panel connector.

TRUE = Writes a trigger signal
FALSE = Does not write a trigger signal
User Command U8 Control Configures the clock, ADC, sampling, and other settings for your device. Use this signal in conjunction with the User Data 0 and User Data 1 signals to select values for these settings. Then apply these settings by selecting the User Command Commit signal. Refer to the User Command Table for more information about values for this signal.
User Command Commit Bool Control A low-to-high transition applies the settings configured with the User Command signal.
User Command Idle Bool Indicator A TRUE value indicates that the device is prepared to accept more commands from the User Command signal.
User Data 0 U8 Control Use this signal in conjunction with the User Data 1 and the User Command signals to configure your device. Refer to the User Command Table for more information about values for this signal.
User Data 1 U8 Control Use this signal in conjunction with the User Data 0 and the User Command signals to configure your device. Refer to the User Command Table for more information about values for this signal.
User Command Status U8 Indicator Indicates whether the previous command completed successfully.

0 = Successful
Nonzero = Unsuccessful
User Return U16 Indicator Returns data configured by the User Command signal.
User Error U8 Indicator Indicates that an error occurred and you must reinitialize the device.

0 = No error
Nonzero = Error
DIO Port 0 Rd Data1 U8 Indicator Reads digital data through the AUX I/O connector on DIO Port 0 channels <0..3>. Bit 0 corresponds with DIO Port 0 (0), bit 1 corresponds with DIO Port 0 (1), and so on. The top four bits of the U8 are unused.
DIO Port 0 Wr Data1 U8 Control Writes digital data through the AUX I/O connector on DIO Port 0 channels <0..3>. Bit 0 corresponds with DIO Port 0 (0), bit 1 corresponds with DIO Port 0 (1), and so on. The top four bits of the U8 are unused.
DIO Port 0 WE1 Bool Control Configures DIO Port 0 channels <0..3> on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
DIO Port 1 Rd Data1 U8 Indicator Reads digital data through the AUX I/O connector on DIO Port 1 channels <0..3>. Bit 0 corresponds with DIO Port 1 (0), bit 1 corresponds with DIO Port 1 (1), and so on. The top four bits of the U8 are unused.
DIO Port 1 Wr Data1 U8 Control Writes digital data through the AUX I/O connector on DIO Port 1 channels <0..3>. Bit 0 corresponds with DIO Port 1 (0), bit 1 corresponds with DIO Port 1 (1), and so on. The top four bits of the U8 are unused.
DIO Port 1 WE1 Bool Control Configures DIO Port 1 channels <0..3> on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 0 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 0.
PFI 0 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 0 if the PFI 0 WE signal is set to TRUE.
PFI 0 WE1 Bool Control Configures PFI 0 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 1 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 1.
PFI 1 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 1 if the PFI 1 WE signal is set to TRUE.
PFI 1 WE1 Bool Control Configures PFI 1 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 2 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 2.
PFI 2 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 2 if the PFI 2 WE signal is set to TRUE.
PFI 2 WE1 Bool Control Configures PFI 2 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 3 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 3.
PFI 3 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 3 if the PFI 3 WE signal is set to TRUE.
PFI 3 WE1 Bool Control Configures PFI 3 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
SPI Idle Bool Indicator Indicates when the SPI interface to either the clock circuit or ADC is being accessed. To use the SPI signals, you must wait for this signal to be TRUE.
SPI Device Select U8 Control Selects which SPI device to interact with. Do not write data to any undefined device. The SPI devices have the following values:

0 = ADC

1 = Clock circuit

2 = PLL circuit

3 = Frequency adjust DAC

5 = Calibration EEPROM
SPI Address U16 Control Configures the SPI address to read and write data.
SPI Read Data U8 Indicator Configures the SPI data to read from a selected device at a SPI address.
SPI Read Bool Control Executes the settings of the SPI Read Data signal when this signal is on a FALSE-to-TRUE transition.
SPI Write Data U32 Control Configures the SPI data to write to a selected device at a SPI address.
SPI Write Bool Control Executes the settings of the SPI Write Data signal when this signal is on a FALSE-to-TRUE transition.
Clock 40 MHz Clock You must select a 40 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality. Access only the User Command and SPI signals in this clock domain.
Clock 200 MHz Clock You must select a 200 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality.
Data Clock Constant clock The FPGA clock used to sample analog input data. In real-time sampling mode, eight samples from each analog input channel are valid on every rising edge of this clock. In TIS mode, 16 samples from only one analog input channel are valid on each clock cycle. During TIS mode, the data in the CLIP signals appears to be coming from both AI 0 and AI 1, but one channel is returning time-interleaved samples for the other channel, which provides 16 total samples on one channel. Refer to the User Command Table to learn how to configure one channel for TIS mode. Access only the analog input and over range signals in this clock domain.
Data Clock 2x Reserved

1 All DIO and PFI signals can be accessed in any clock domain, but you still must comply with the physical clock capabilities of your device.

NI 5771 CLIP Clocks

The following table describes the NI 5771 CLIP clock signals.

CLIP Signal Name Description
CLK40 You must select a 40 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality. Access only the User Command and SPI signals in this clock domain.
CLK200 You must select a 200 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality.
Data Clock2 The FPGA clock used to sample analog input data. In real-time sampling mode, eight samples from each analog input channel are valid on every rising edge of this clock. In TIS mode, 16 samples from only one analog input channel are valid on each clock cycle. During TIS mode, the data in the CLIP signals appears to be coming from both AI 0 and AI 1, but one channel is returning time-interleaved samples for the other channel, which provides 16 total samples on one channel. Refer to the User Command Table to learn how to configure one channel for TIS mode. Access only the analog input and over range signals in this clock domain.
Data Clock 2x2 Unused. Reserved for future use and internal use.

The Data Clock and Data Clock 2x signals are only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
3.0 and later 4.0 and later Data Clock and Data Clock 2x
1.0 and earlier 3.4 and earlier IO Module Clock 0 and IO Module Clock 1

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