NI 5772 Synchronized Reference Clock CLIP

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP is the NI 5772 Terminal Block, and it provides FlexRIO Instrument Development Library (FIDL) synchronization using a 10 MHz reference. This CLIP also provides access to two analog input channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:

  • Internal Sample Clock
  • Internal Sample Clock locked to an external Reference Clock through the REF IN connector
  • Internal Sample Clock locked to an external Reference Clock through IoModSyncClock

This CLIP also contains an engine to program the ADC and the phase-locked loop (PLL), either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup. In the LabVIEW FPGA Module, 8-bit analog input data is accessed using a U8 data type (left-justified). The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal. The four PFI signals are accessed individually using Boolean signals.

Although real-time sampling is the default sampling mode on the NI 5772, the NI 5772 CLIP also supports Time Interleaved Sampling (TIS). TIS enables the device to use both channels on the ADC to sample the same waveform at different relative phases, which increases the real-time sample rate. The NI 5772 then interleaves the samples to create a waveform as if only one ADC channel were sampling the waveform at twice the Sample Clock rate. The NI 5772 supports three TIS modes:

  • Channel 0 sampling only
  • Channel 1 sampling only
  • Dual-TIS mode, which samples Channel 0 and Channel 1 simultaneously. Dual-TIS mode has more bandwidth than the other TIS modes.
Note Note  The ADC data sheet refers to TIS as dual-edge sampling (DES).

To configure the NI 5772 for TIS mode using this CLIP, refer to the User Command Table.

In TIS mode, the data is returned on both the AI 0 Data <N-3..N> and AI 1 Data <N-3..N> signals even though the device is only sampling the single analog input channel. The first sample of data is always AI 1 Data N-3, regardless of the channel sample. The following figure demonstrates TIS on an NI 5772 device.

5772 TIS Mode

The NI 5772 allows you to configure the clock, ADC, sampling and other settings using the NI LabVIEW FPGA Module software.

  • Use the User Command, User Data 0, and User Data 1 signals to configure these settings.
  • Use the User Command Commit signal to apply these settings.
  • Use the User Return signal to read configured settings.
  • Use the User Command Status signal to determine whether the previous command was expected successfully.
  • Use the User Error signal to determine if you must reinitialize the device due to an error.

Refer to the User Command Table for more information about values for these signals.

User Command Table

User Setting User Command Value (U8) User Data 0 Value (U16) User Data 1 Value (U8) User Return Value (U8)
Clock Selection Enumeration 0 0 = Internal Sample Clock

1 = Internal Sample Clock locked to an external Reference Clock through the CLK IN connector

2 = External Sample Clock through the CLK IN connector

3 = Internal Sample Clock locked to an external Reference Clock through Sync Clock
N/A N/A
ADC Self-Calibration 1 Performs a self-calibration on the ADC12D800RF. N/A N/A
Set TIS Mode 4 0 = TIS mode disabled
1 = TIS mode (Channel 0 only) enabled
2 = TIS mode (Channel 1 only) enabled
3 = Dual-TIS Mode (Channels 0 and 1) enabled
Note Note  DC-coupled modules do not support Dual-TIS Mode.
N/A N/A
Count Metastability 5 Issues 1,000 timestamp measurements and returns the number of timestamps that are metastable. N/A N/A
Set Timestamp Source 6 Selects the source of the timestamp measurement. N/A N/A
Read Revision 240 Reads the CLIP revision number. N/A N/A
Read Oldest Compatible Revision 242 Reads the CLIP Oldest Compatible Revision number. N/A N/A
Reinitialize 255 Configures the NI 5772 to its default power on configuration. N/A N/A
Note Note  To use the SPI address and data signals to program the NI 5772 ADC and clock circuit, you must refer to the register map provided in each respective component datasheet. Refer to the NI 5772R User Manual and Specifications document included with your device for the part numbers for the NI 5772 ADC and clock circuit.

Example Projects

The FlexRIO driver installation includes the following example projects to help get you started with the NI 5772 CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example projects use the I/O signals exposed by the NI 5772 CLIP:

  • AC-coupled
    • NI 5772 - Clock Select.lvproj—This example demonstrates how to select the desired clock configuration for the NI 5772 adapter module. This example continuously acquires records of analog input data from the NI 5772 and allows you to select an AI channel, trigger type, and record size.
    • NI 5772 - Getting Started.lvproj—This example continuously acquires records of analog input data from the NI 5772 and allows you to select an AI channel, trigger type, and record size.
    • NI 5772 - TIS Mode Enabled.lvproj—This example demonstrates how to enable Time Interleaved Sampling (TIS) with the NI 5772 to achieve a sampling rate of 1.6 GS/s. The example continuously acquires records of analog input data from the NI 5772 and allows you to select an AI channel, trigger type, and record size.
  • DC-coupled
    • NI 5772 - Clock Select.lvproj—This example demonstrates how to select the desired clock configuration for the NI 5772 adapter module. This example continuously acquires records of analog input data from the NI 5772 and allows you to select an AI channel, trigger type, and record size.
    • NI 5772 - Getting Started.lvproj—This example continuously acquires records of analog input data from the NI 5772 and allows you to select an AI channel, trigger type, and record size.
    • NI 5772 - TIS Mode Enabled.lvproj—This example demonstrates how to enable Time Interleaved Sampling (TIS) with the NI 5772 to achieve a sampling rate of 1.6 GS/s. The example continuously acquires records of analog input data from the NI 5772 and allows you to select an AI channel, trigger type, and record size.

For more information about the NI 5772, refer to the NI 5772R User Manual and Specifications document available at ni.com/manuals.

CLIP I/O Signals

CLIP Signal Name Data Type Control/Indicator Required Clock Domain Description
AI 0 Data N-3 I16 Indicator Data Clock Returns analog input data through the AI 0 front panel connector. Each sample is a left-justified I16 data type. If AI 0 is configured for TIS mode, these signals return time-interleaved samples for AI 0.
AI 0 Data N-2
AI 0 Data N-1
AI 0 Data N
AI 1 Data N-3 I16 Indicator Data Clock Returns analog input data through the AI 1 front panel connector. Each sample is a left-justified I16 data type. If AI 1 is configured for TIS mode, these signals return time-interleaved samples for AI 1.
AI 1 Data N-2
AI 1 Data N-1
AI 1 Data N
AI 0 Over Range N-3 Bool Indicator Data Clock A TRUE value indicates that the input signal on the AI 0 front panel connector is beyond the full-scale range. This signal is synchronous to the analog input data.
AI 0 Over Range N-2
AI 0 Over Range N-1
AI 0 Over Range N
AI 1 Over Range N-3 Bool Indicator Data Clock A TRUE value indicates that the input signal on the AI 1 front panel connector is beyond the full-scale range. This signal is synchronous to the analog input data.
AI 1 Over Range N-2
AI 1 Over Range N-1
AI 1 Over Range N
Initialization Done Bool Indicator Clock 40 MHz A TRUE value indicates that the device has finished its configuration and the sampled data is valid.
PLL Locked Bool Indicator Clock 40 MHz A TRUE value indicates that the PLL is locked. This signal is valid only when using a Reference Clock, either through the CLK IN connector or through the Sync Clock. If you are not using a Reference Clock, this signal is FALSE.
User Command U8 Control Clock 40 MHz Configures the clock, ADC, sampling, and other settings for your device. Use this signal with the User Data 0 and User Data 1 signals to select values for these settings. Apply these settings by selecting the User Command Commit signal. Refer to the User Command Table for more information about values for this signal.
User Command Commit Bool Control Clock 40 MHz Applies the settings configured with the User Command signal.
User Command Idle Bool Indicator Clock 40 MHz A TRUE value indicates that the device is prepared to accept more commands from the User Command signal.
User Data 0 U16 Control Clock 40 MHz Use this signal with the User Data 1 and User Command signals to configure your device. Refer to the User Command Table for more information about values for this signal.
User Data 1 U8 Control Clock 40 MHz Use this signal with the User Data 0 and User Command signals to configure your device. Refer to the User Command Table for more information about values for this signal.
User Command Status U8 Indicator Clock 40 MHz Indicates status of the previous command.

0 = Successful
1 = The command does not exist
2 = Option does not exist
3 = The SPI device is undefined
User Return U32 Indicator Clock 40 MHz Returns data configured by the User Command signal.
User Error U8 Indicator Clock 40 MHz Indicates that an error occurred and you must reinitialize the device.
Asynchronous Trigger Input Bool Indicator Indicates whether the FPGA received an unclocked trigger signal from the TRIG front panel connector.

TRUE = The FPGA has received a trigger signal
FALSE = The FPGA has not received a trigger signal
Synchronous Trigger Input N-3 Bool Indicator Data Clock Indicates, per clock cycle, the time that the FPGA received a trigger signal from the TRIG front panel connector in relation to the samples taken. Although synchronous to the ADC data, the latency through the trigger is different than the ADC. The buffers in the trigger path limit the bandwidth of like signals to less than 320 MB/s.
Synchronous Trigger Input N-2
Synchronous Trigger Input N-1
Synchronous Trigger Input N
Trigger Output Bool Control Specifies whether to write a trigger signal through the TRIG front panel connector.

TRUE = Writes a trigger signal
FALSE = Does not write a trigger signal
Trigger WE Bool Control Configures the TRIG front panel connector to either read or write a trigger signal.

TRUE = Enables the Trigger Output signal
FALSE = Enables the Asynchronous Trigger Input and the Synchronous Trigger Input signals
DIO Port 0 Rd Data1 U8 Indicator Reads digital data through the AUX I/O connector on DIO Port 0 channels <0..3>. Bit 0 corresponds with DIO Port 0 (0), bit 1 corresponds with DIO Port 0 (1), and so on. The upper four bits of the U8 are unused.
DIO Port 0 Wr Data1 U8 Control Writes digital data through the AUX I/O connector on DIO Port 0 channels <0..3>. Bit 0 corresponds with DIO Port 0 (0), bit 1 corresponds with DIO Port 0 (1), and so on. The upper four bits of the U8 are unused.
DIO Port 0 WE Request1 Bool Control Requests the DIO Port 0 channels <0..3> on the AUX I/O connector for reading or writing.

TRUE = Write enable requested
FALSE = Write disable requested (output tristated)
DIO Port 0 WE Actual1 Bool Indicator Indicates the current configuration of the DIO Port 0 channels <0..3> on the AUX I/O connector.

TRUE = Writing enabled
FALSE = Writing disabled (output tristated)
DIO Port 1 Rd Data1 U8 Indicator Reads digital data through the AUX I/O connector on DIO Port 1 channels <0..3>. Bit 0 corresponds with DIO Port 1 (0), bit 1 corresponds with DIO Port 1 (1), and so on. The upper four bits of the U8 are unused.
DIO Port 1 Wr Data1 U8 Control Writes digital data through the AUX I/O connector on DIO Port 1 channels <0..3>. Bit 0 corresponds with DIO Port 1 (0), bit 1 corresponds with DIO Port 1 (1), and so on. The upper four bits of the U8 are unused.
DIO Port 1 WE Request1 Bool Control Requests the DIO Port 1 channels <0..3> on the AUX I/O connector to be configured for reading or writing.

TRUE = Writing requested
FALSE = Reading requested (output tristated)
DIO Port 1 WE Actual1 Bool Indicator Indicates the current configuration of the DIO Port 1 channels <0..3> on the AUX I/O connector.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 0 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 0 when set to TRUE.
PFI 0 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 0 if the PFI 0 WE signal is set to TRUE.
PFI 0 WE1 Bool Control Configures PFI 0 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 1 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 1 when set to TRUE.
PFI 1 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 1 if the PFI 1 WE signal is set to TRUE.
PFI 1 WE1 Bool Control Configures PFI 1 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 2 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 2 when set to TRUE.
PFI 2 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 2 if the PFI 2 WE signal is set to TRUE.
PFI 2 WE1 Bool Control Configures PFI 2 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
PFI 3 Rd Data1 Bool Indicator Reads digital data through the AUX I/O connector on PFI 3 when set to TRUE.
PFI 3 Wr Data1 Bool Control Writes digital data through the AUX I/O connector on PFI 3 if the PFI 3 WE signal is set to TRUE.
PFI 3 WE1 Bool Control Configures PFI 3 on the AUX I/O connector for reading or writing.

TRUE = Writing enabled
FALSE = Reading enabled (output tristated)
SPI Idle Bool Indicator Clock 40 MHz Indicates when the SPI interface to the clock circuit or ADC is being accessed. To use the SPI signals, you must wait for this signal to be TRUE.
SPI Device Select U8 Control Clock 40 MHz Selects which SPI device to interact with. Write data only to a defined device. The SPI devices have the following values:

0 = ADC

1 = PLL circuit

SPI Address U16 Control Clock 40 MHz Configures the SPI address to read and write data. Write data only to addresses supported by the selected device.
SPI Write Data U32 Control Clock 40 MHz Configures the SPI data to write to a selected device at a SPI address.
SPI Read Data U32 Indicator Clock 40 MHz Configures the SPI data to read from a selected device at a SPI address.
SPI Read Bool Control Clock 40 MHz Executes the settings of the SPI Read Data signal when this signal is on a FALSE-to-TRUE transition.
SPI Write Bool Control Clock 40 MHz Executes the settings of the SPI Write Data signal when this signal is on a FALSE-to-TRUE transition.
Clock 40 MHz Clock N/A You must select a 40 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality. Access the User Command and SPI signals only in this clock domain.
Clock 200 MHz Clock N/A You must select a 200 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality.
Data Clock Constant Clock FPGA clock used to sample analog input data. In real-time sampling mode, eight samples from each analog input channel are valid on every rising edge of this clock. In TIS mode, 16 samples from the analog input channel(s) are valid on each clock cycle. During single-channel TIS mode, the data in the CLIP signals appears to come from both AI 0 and AI 1, but one channel is returning time-interleaved samples for the other channel, which provides eight total samples on one channel. During dual-TIS mode, the data comes from both channels simultaneously. Refer to the User Command signals to learn how to configure one channel for TIS mode. You should only access the analog input, synchronized trigger input, and over range signals in this clock domain.
Data Clock 2x Constant Clock Indicator N/A Unused. Reserved for future use and internal use.

1 All DIO and PFI signals can be accessed in any clock domain, but you still must comply with the physical clock capabilities of your device.

NI 5772 Synchronous Reference Clock CLIP Clocks

The following table describes the NI 5772 Synchronous Reference Clock CLIP clock signals.

CLIP Signal Name Description
CLK40 You must select a 40 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality. The following signals should only be accessed in this clock domain: Module Ready, Reinitialize, Sample Clock Select, Sample Clock Commit, and all SPI signals.
CLK200 You must select a 200 MHz clock in the Clock Selections category of the IO Module Properties dialog box for proper CLIP functionality.
Data Clock2 FPGA clock used to sample analog input data. In real-time sampling mode, eight samples from each analog input channel are valid on every rising edge of this clock. In TIS mode, 16 samples from the analog input channel(s) are valid on each clock cycle. During single-channel TIS mode, the data in the CLIP signals appears to come from both AI 0 and AI 1, but one channel is returning time-interleaved samples for the other channel, which provides eight total samples on one channel. During dual-TIS mode, the data comes from both channels simultaneously. Refer to the User Command signals to learn how to configure one channel for TIS mode. You should only access the analog input, synchronized trigger input, and over range signals in this clock domain.
Data Clock 2x2 Unused. Reserved for future use and internal use.

2 The Data Clock and Data Clock 2x signals are only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
2.0 and later 4.0 and later Data Clock and Data Clock 2x
1.2.1 and earlier 3.4 and earlier IO Module Clock 0 and IO Module Clock 1

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