NI 6583 Channel CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels using a simple channel-based interface in which each I/O and direction control is represented as a Boolean signal in LabVIEW FPGA. This CLIP provides a clock signal and a polarity control for export to each DDC connector. The clock input signals from the DDC connectors are passed to LabVIEW FPGA for use in the FPGA VI.

This CLIP allows you to export a clock on each DDC connector. LabVIEW generates this clock, which you can invert before it is exported. Inverting this clock allows you to synchronize the generated data to either the rising or falling edge of the clock. Setting the invert clock signal to FALSE synchronizes data to the rising edge, and setting the invert clock signal to TRUE synchronizes data to the falling edge.

Note Note  LabVIEW FPGA treats NI 6583 Channel CLIP signals as asynchronous by inserting synchronization registers by default.

Example Projects

FlexRIO support installation includes example projects to help get you started with the NI 6583 DDR Connector CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example projects use the I/O signals exposed by the NI 6583 DDR Connector CLIP:

  • NI 6583 Cont Acq with FIFO-Internal Clock.lvproj—This example acquires digital data from the two DDC connectors of the NI 6583. The acquisition sample rate is 80 MHz.
  • NI 6583 Continuous Acquisition DDR - External Clock.lvproj—This example acquires digital data from the two DDC connectors of the NI 6583. The acquisition sample rate is 100 MHz.
  • NI 6583 Continuous Generation - Internal Clock.lvproj—This example continuously generates data on the DDC A and DDC B connectors of the NI 6583. The generation data rate is 100 MHz.
  • NI 6583 Continuous Generation DDR-Internal Clock.lvproj—This example continuously generates data on the DDC A and DDC B connectors of the NI 6583. The data generation rate is 100 MHz.
  • NI 6583 Finite Acquisition and Generation-Simple.lvproj—This example generates either a constant value or a digital count-up pattern on the first eight even numbered channels of the DDC A and DDC B connectors on the NI 6583, and then acquires back that pattern on the first eight odd numbered channels of the DDC A and DDC B connectors.

For more information about using an example project to get started with the NI 6583, refer to the NI 6583R User Guide and Specifications document, shipped with your device and available at ni.com/manuals.

CLIP I/O Signals

The following table describes the NI 6583 Channel CLIP I/O signals.

CLIP Signal Name

(DDCA Connector; DDCB Connector)
Description NI 6583 Connector Data Type NI 6583 Connector Signal
SE_Ch0_Dir Direction control. Write only.

TRUE = Generation

FALSE = Acquisition
DDC A Bool DIO 0
SE_Ch1_Dir DIO 1
SE_Ch2_Dir DIO 2
SE_Ch3_Dir DIO 3
SE_Ch4_Dir DIO 4
SE_Ch5_Dir DIO 5
SE_Ch6_Dir DIO 6
SE_Ch7_Dir DIO 7
SE_Ch8_Dir DIO 8
SE_Ch9_Dir DIO 9
SE_Ch10_Dir DIO 10
SE_Ch11_Dir DIO 11
SE_Ch12_Dir DIO 12
SE_Ch13_Dir DIO 13
SE_Ch14_Dir DIO 14
SE_Ch15_Dir DIO 15
SE_Ch16_Dir DIO 16
SE_Ch17_Dir DIO 17
SE_Ch18_Dir DIO 18
SE_Ch19_Dir DIO 19
SE_Ch20_Dir DIO 20
SE_Ch21_Dir DIO 21
SE_Ch22_Dir DIO 22
SE_Ch23_Dir DIO 23
SE_Ch24_Dir DIO 24
SE_Ch25_Dir DIO 25
SE_Ch26_Dir DIO 26
SE_Ch27_Dir DIO 27
SE_Ch28_Dir DIO 28
SE_Ch29_Dir DIO 29
SE_Ch30_Dir DIO 30
SE_Ch31_Dir DIO 31
SE_Ch0_Rd Single-ended acquisition channel. Read only. DDC A Bool DIO 0
SE_Ch1_Rd DIO 1
SE_Ch2_Rd DIO 2
SE_Ch3_Rd DIO 3
SE_Ch4_Rd DIO 4
SE_Ch5_Rd DIO 5
SE_Ch6_Rd DIO 6
SE_Ch7_Rd DIO 7
SE_Ch8_Rd DIO 8
SE_Ch9_Rd DIO 9
SE_Ch10_Rd DIO 10
SE_Ch11_Rd DIO 11
SE_Ch12_Rd DIO 12
SE_Ch13_Rd DIO 13
SE_Ch14_Rd DIO 14
SE_Ch15_Rd DIO 15
SE_Ch16_Rd DIO 16
SE_Ch17_Rd DIO 17
SE_Ch18_Rd DIO 18
SE_Ch19_Rd DIO 19
SE_Ch20_Rd DIO 20
SE_Ch21_Rd DIO 21
SE_Ch22_Rd DIO 22
SE_Ch23_Rd DIO 23
SE_Ch24_Rd DIO 24
SE_Ch25_Rd DIO 25
SE_Ch26_Rd DIO 26
SE_Ch27_Rd DIO 27
SE_Ch28_Rd DIO 28
SE_Ch29_Rd DIO 29
SE_Ch30_Rd DIO 30
SE_Ch31_Rd DIO 31
SE_Ch0_Wr Single-ended generation channel. Write only. DDC A Bool DIO 0
SE_Ch1_Wr DIO 1
SE_Ch2_Wr DIO 2
SE_Ch3_Wr DIO 3
SE_Ch4_Wr DIO 4
SE_Ch5_Wr DIO 5
SE_Ch6_Wr DIO 6
SE_Ch7_Wr DIO 7
SE_Ch8_Wr DIO 8
SE_Ch9_Wr DIO 9
SE_Ch10_Wr DIO 10
SE_Ch11_Wr DIO 11
SE_Ch12_Wr DIO 12
SE_Ch13_Wr DIO 13
SE_Ch14_Wr DIO 14
SE_Ch15_Wr DIO 15
SE_Ch16_Wr DIO 16
SE_Ch17_Wr DIO 17
SE_Ch18_Wr DIO 18
SE_Ch19_Wr DIO 19
SE_Ch20_Wr DIO 20
SE_Ch21_Wr DIO 21
SE_Ch22_Wr DIO 22
SE_Ch23_Wr DIO 23
SE_Ch24_Wr DIO 24
SE_Ch25_Wr DIO 25
SE_Ch26_Wr DIO 26
SE_Ch27_Wr DIO 27
SE_Ch28_Wr DIO 28
SE_Ch29_Wr DIO 29
SE_Ch30_Wr DIO 30
SE_Ch31_Wr DIO 31
SE_PFI1_Dir Direction control. Write only.

TRUE = Generation

FALSE = Acquisition
DDC A Bool PFI 1
SE_PFI2_Dir PFI 2
SE_PFI3_Dir PFI 3
SE_PFI1_Rd Single-ended acquisition channel. Read only. DDC A Bool PFI 1
SE_PFI2_Rd PFI 2
SE_PFI3_Rd PFI 3
SE_PFI1_Wr Single-ended generation channel. Write only. DDC A Bool PFI 1
SE_PFI2_Wr PFI 2
SE_PFI3_Wr PFI 3
SE_ClockOut Single-ended exported clock. Write only. DDC A Bool DDC CLK OUT
SE_ClockOut_Invert Single-ended exported clock polarity control. Write only.

TRUE = Inverted

FALSE = Noninverted
DDC A Bool DDC CLK OUT
SE_ClockOut_En Single-ended exported clock enable. Write only.

TRUE = Exported to DDC connector

FALSE = Tristated output
DDC A Bool DDC CLK OUT
LVDS_Ch0_Dir Direction control. Write only.

TRUE = Generation

FALSE = Acquisition
DDC B Bool DIO 0+, DIO 0–
LVDS_Ch1_Dir DIO 1+, DIO 1–
LVDS_Ch2_Dir DIO 2+, DIO 2–
LVDS_Ch3_Dir DIO 3+, DIO 3–
LVDS_Ch4_Dir DIO 4+, DIO 4–
LVDS_Ch5_Dir DIO 5+, DIO 5–
LVDS_Ch6_Dir DIO 6+, DIO 6–
LVDS_Ch7_Dir DIO 7+, DIO 7–
LVDS_Ch8_Dir DIO 8+, DIO 8–
LVDS_Ch9_Dir DIO 9+, DIO 9–
LVDS_Ch10_Dir DIO 10+, DIO 10–
LVDS_Ch11_Dir DIO 11+, DIO 11–
LVDS_Ch12_Dir DIO 12+, DIO 12–
LVDS_Ch13_Dir DIO 13+, DIO 13–
LVDS_Ch14_Dir DIO 14+, DIO 14–
LVDS_Ch15_Dir DIO 15+, DIO 15–
LVDS_Ch0_Rd LVDS acquisition channel. Read only. DDC B Bool DIO 0+, DIO 0–
LVDS_Ch1_Rd DIO 1+, DIO 1–
LVDS_Ch2_Rd DIO 2+, DIO 2–
LVDS_Ch3_Rd DIO 3+, DIO 3–
LVDS_Ch4_Rd DIO 4+, DIO 4–
LVDS_Ch5_Rd DIO 5+, DIO 5–
LVDS_Ch6_Rd DIO 6+, DIO 6–
LVDS_Ch7_Rd DIO 7+, DIO 7–
LVDS_Ch8_Rd DIO 8+, DIO 8–
LVDS_Ch9_Rd DIO 9+, DIO 9–
LVDS_Ch10_Rd DIO 10+, DIO 10–
LVDS_Ch11_Rd DIO 11+, DIO 11–
LVDS_Ch12_Rd DIO 12+, DIO 12–
LVDS_Ch13_Rd DIO 13+, DIO 13–
LVDS_Ch14_Rd DIO 14+, DIO 14–
LVDS_Ch15_Rd DIO 15+, DIO 15–
LVDS_Ch0_Wr LVDS generation channel. Write only. DDC B Bool DIO 0+, DIO 0–
LVDS_Ch1_Wr DIO 1+, DIO 1–
LVDS_Ch2_Wr DIO 2+, DIO 2–
LVDS_Ch3_Wr DIO 3+, DIO 3–
LVDS_Ch4_Wr DIO 4+, DIO 4–
LVDS_Ch5_Wr DIO 5+, DIO 5–
LVDS_Ch6_Wr DIO 6+, DIO 6–
LVDS_Ch7_Wr DIO 7+, DIO 7–
LVDS_Ch8_Wr DIO 8+, DIO 8–
LVDS_Ch9_Wr DIO 9+, DIO 9–
LVDS_Ch10_Wr DIO 10+, DIO 10–
LVDS_Ch11_Wr DIO 11+, DIO 11–
LVDS_Ch12_Wr DIO 12+, DIO 12–
LVDS_Ch13_Wr DIO 13+, DIO 13–
LVDS_Ch14_Wr DIO 14+, DIO 14–
LVDS_Ch15_Wr DIO 15+, DIO 15–
LVDS_PFI1_Dir Direction control. Write only.

TRUE = Generation

FALSE = Acquisition
DDC B Bool PFI 1+, PFI 1–
LVDS_PFI2_Dir PFI 2+, PFI 2–
LVDS_PFI3_Dir PFI 3+, PFI 3–
LVDS_PFI1_Rd LVDS acquisition channel. Read only. DDC B Bool PFI 1+, PFI 1–
LVDS_PFI2_Rd PFI 2+, PFI 2–
LVDS_PFI3_Rd PFI 3+, PFI 3–
LVDS_PFI1_Wr LVDS generation channel. Write only. DDC B Bool PFI 1+, PFI 1–
LVDS_PFI2_Wr PFI 2+, PFI 2–
LVDS_PFI3_Wr PFI 3+, PFI 3–
LVDS_ClockOut LVDS exported clock. Write only. DDC B Bool DDC CLK OUT+, DDC CLK OUT–
LVDS_ClockOut_Invert LVDS exported clock polarity control. Write only.

TRUE = Inverted

FALSE = Noninverted
DDC B Bool DDC CLK OUT+, DDC CLK OUT–
LVDS_ClockOut_En LVDS exported clock enable. Write only.

TRUE = Exported to DDC connector

FALSE = Tristated output
DDC B Bool DDC CLK OUT+, DDC CLK OUT–
Voltage_Family Enumerated type for selection of typical voltage levels of the VCC:

0 = 1.2 V

1 = 1.5 V

2 = 1.8 V

3 = 2.5 V

4 = 3.3 V

Write only.
U8
Set_Voltage_Family Latches the value from Voltage_Family on a FALSE-to-TRUE transition into the VCC supply.

Write only.
Bool
Voltage_DAC Controls the value of the VCC with a 10-bit DAC word. Refer to the NI 6583R User Guide and Specifications document for gain, offset, and valid voltage range specifications.

Write only.
U16
Set_Voltage_DAC Latches the value from Voltage_DAC on a FALSE-to-TRUE transition into the VCC supply.

Write only.
Bool
Set_Voltage_Done Signals when the VCC voltage access has completed. Do not operate this device until this value is TRUE.

Read only.
Bool
DCM_Locked Signals the locked status of the internal digital clock manager (DCM). When this value is FALSE, the DCM is unlocked and requires a resetting or reloading of the FPGA. Failure to lock the DCM may result in direction control failure.

Read only.
Bool
DDC_A_Strobe External single-ended Sample Clock source that can be used as an FPGA base clock. DDC A Bool STROBE
DDC_B_Strobe External LVDS Sample Clock source that can be used as an FPGA Base clock. DDC B Bool STROBE+, STROBE–
Voltage_Control_Clock Clock used to drive voltage control state machine. This clock must be connected to the 40 MHz Onboard clock. Bool

NI 6583 Channel CLIP Clocks

The following table describes the NI 6583 Channel CLIP clock signals.

CLIP Signal Name Description
DDC_A_Strobe* External single-ended Sample Clock source that can be used as an FPGA base clock.
DDC_B_Strobe* External LVDS Sample Clock source that can be used as an FPGA base clock.
*DDC_A_Strobe and DDC_B_Strobe are only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
14.1 and later FlexRIO Adapter Module Support 14.1 and later DDC_A_Strobe and DDC_B_Strobe
1.2 and earlier FlexRIO Adapter Module Support 14.0 and earlier IO Module Clock 0 and IO Module Clock 1

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