NI 6583 Basic Connector CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels on each connector, where the channels are grouped per connector. This CLIP has 48 data lines, six PFI lines, two clock input signals, and two clock output signals, and it allows for individual clock output inversion. The single-ended data and direction lines on DDC A are accessed using a U32 data type (for reads, writes, and direction control). The LVDS data and direction lines on DDC B are accessed using a U16 data type (for reads, writes, and direction control). This CLIP provides a clock signal and a polarity control for export to each DDC connector. The clock input signals from the DDC connectors are passed to LabVIEW FPGA for use in the FPGA VI.

This CLIP allows you to export a clock on each DDC connector. LabVIEW generates this clock, which you can invert before it is exported. Inverting this clock allows you to synchronize the generated data to either the rising or falling edge of the clock. Setting the invert clock signal to FALSE synchronizes data to the rising edge, and setting the invert clock signal to TRUE synchronizes data to the falling edge.

Note Note  LabVIEW FPGA treats NI 6583 Connector CLIP signals as asynchronous by inserting synchronization registers by default.

Example Projects

FlexRIO support installation includes example projects to help get you started with the NI 6583 DDR Connector CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example projects use the I/O signals exposed by the NI 6583 DDR Connector CLIP:

  • NI 6583 Cont Acq with FIFO-Internal Clock.lvproj—This example acquires digital data from the two DDC connectors of the NI 6583. The acquisition sample rate is 80 MHz.
  • NI 6583 Continuous Acquisition DDR - External Clock.lvproj—This example acquires digital data from the two DDC connectors of the NI 6583. The acquisition sample rate is 100 MHz.
  • NI 6583 Continuous Generation - Internal Clock.lvproj—This example continuously generates data on the DDC A and DDC B connectors of the NI 6583. The generation data rate is 100 MHz.
  • NI 6583 Continuous Generation DDR-Internal Clock.lvproj—This example continuously generates data on the DDC A and DDC B connectors of the NI 6583. The data generation rate is 100 MHz.
  • NI 6583 Finite Acquisition and Generation-Simple.lvproj—This example generates either a constant value or a digital count-up pattern on the first eight even numbered channels of the DDC A and DDC B connectors on the NI 6583, and then acquires back that pattern on the first eight odd numbered channels of the DDC A and DDC B connectors.

For more information about using an example project to get started with the NI 6583, refer to the NI 6583R User Guide and Specifications document, shipped with your device and available at ni.com/manuals.

CLIP I/O Signals

The following table describes the NI 6583 Connector CLIP I/O signals.

CLIP Signal Name

(DDCA Connector; DDCB Connector)
Description NI 6583 Connector Data Type Bit NI 6583 Connector Signal
SE_Data_Dir Single-ended direction control. Write only.

0 = I/O acquires

1 = I/O generates
DDC B U16 0 DIO 0
1 DIO 1
SE_Data_Rd Single-ended acquisition. Read only. 2 DIO 2
3 DIO 3
SE_Data_Wr Single-ended generation. Write only. 4 DIO 4
5 DIO 5
6 DIO 6
7 DIO 7
8 DIO 8
9 DIO 9
10 DIO 10
11 DIO 11
12 DIO 12
13 DIO 13
14 DIO 14
15 DIO 15
16 DIO 16
17 DIO 17
18 DIO 18
19 DIO 19
20 DIO 20
21 DIO 21
22 DIO 22
23 DIO 23
24 DIO 24
25 DIO 25
26 DIO 26
27 DIO 27
28 DIO 28
29 DIO 29
30 DIO 30
31 DIO 31
SE_PFI1_Dir Direction control. Write only.

TRUE = Generation

FALSE = Acquisition
DDC A Bool PFI 1
SE_PFI2_Dir PFI 2
SE_PFI3_Dir PFI 3
SE_PFI1_Rd Single-ended acquisition channel. Read only. DDC A Bool PFI 1
SE_PFI2_Rd PFI 2
SE_PFI3_Rd PFI 3
SE_PFI1_Wr Single-ended generation channel. Write only. DDC A Bool PFI 1
SE_PFI2_Wr PFI 2
SE_PFI3_Wr PFI 3
SE_ClockOut Exported single-ended clock. Write only. DDC A Bool DDC CLK OUT
SE_ClockOut_Invert Exported single-ended clock polarity control. Write only.

TRUE = Inverted

FALSE = Noninverted
DDC A Bool DDC CLK OUT
SE_ClockOut_En Exported single-ended clock enable. Write only.

TRUE = Exported to DDC connector

FALSE = Tristated output
DDC A Bool DDC CLK OUT
LVDS_Data_Dir LVDS direction control. Write only.

0 = I/O acquires

1 = I/O generates
DDC B U16 0 DIO 0+, DIO 0–
1 DIO 1+, DIO 1–
LVDS_Data_Rd LVDS acquisition. Read only. 2 DIO 2+, DIO 2–
3 DIO 3+, DIO 3–
LVDS_Data_Wr LVDS generation. Write only. 4 DIO 4+, DIO 4–
5 DIO 5+, DIO 5–
6 DIO 6+, DIO 6–
7 DIO 7+, DIO 7–
8 DIO 8+, DIO 8–
9 DIO 9+, DIO 9–
10 DIO 10+, DIO 10–
11 DIO 11+, DIO 11–
12 DIO 12+, DIO 12–
13 DIO 13+, DIO 13–
14 DIO 14+, DIO 14–
15 DIO 15+, DIO 15–
LVDS_PFI1_Dir Direction control. Write only.

TRUE = Generation

FALSE = Acquisition
DDC B Bool PFI 1+, PFI 1–
LVDS_PFI2_Dir PFI 2+, PFI 2–
LVDS_PFI3_Dir PFI 3+, PFI 3–
LVDS_PFI1_Rd LVDS acquisition channel. Read only. DDC B Bool PFI 1+, PFI 1–
LVDS_PFI2_Rd PFI 2+, PFI 2–
LVDS_PFI3_Rd PFI 3+, PFI 3–
LVDS_PFI1_Wr LVDS generation channel. Write only. DDC B Bool PFI 1+, PFI 1–
LVDS_PFI2_Wr PFI 2+, PFI 2–
LVDS_PFI3_Wr PFI 3+, PFI 3–
LVDS_ClockOut Exported LVDS clock. Write only. DDC B Bool DDC CLK OUT+, DDC CLK OUT–
LVDS_ClockOut_Invert Exported LVDS clock polarity control. Write only.

TRUE = Inverted

FALSE = Noninverted
DDC B Bool DDC CLK OUT+, DDC CLK OUT–
LVDS_ClockOut_En Exported LVDS clock enable. Write only.

TRUE = Exported to DDC connector

FALSE = Tristated output
DDC B Bool DDC CLK OUT+, DDC CLK OUT–
Voltage_Family Enumerated type for selection of typical voltage levels of the VCC:

0 = 1.2 V

1 = 1.5 V

2 = 1.8 V

3 = 2.5 V

4 = 3.3 V

Write only.
U16
Set_Voltage_Family Latches the value from Voltage_Family on a FALSE-to-TRUE transition into the VCC supply.

Write only.
Bool
Voltage_DAC Controls the value of the VCC with a 10-bit DAC word. Refer to the NI 6583R User Guide and Specifications document for gain, offset, and valid voltage range specifications.

Write only.
U16
Set_Voltage_DAC Latches the value from Voltage_DAC on a FALSE-to-TRUE transition into the VCC supply.

Write only.
Bool
Set_Voltage_Done Signals when the VCC voltage access has completed. Do not operate this device until this value is TRUE.

Read only.
Bool
DCM_Locked Signals the locked status of the internal digital clock manager (DCM). When this value is FALSE, the DCM is unlocked and requires a resetting or reloading of the FPGA. Failure to lock the DCM may result in direction control failure.

Read only.
Bool
DDC_A_Strobe External single-ended Sample Clock source that can be used as an FPGA base clock. DDC A Bool STROBE
DDC_B_Strobe External LVDS Sample Clock source that can be used as an FPGA base clock. DDC B Bool STROBE+, STROBE–
Voltage_Control_Clock Clock used to drive voltage control state machine. This clock must be connected to the 40 MHz Onboard clock. Bool

NI 6583 Basic Connector CLIP Clocks

The following table describes the NI 6583 Basic Connector CLIP clock signals.

CLIP Signal Name Description
DDC_A_Strobe* External single-ended Sample Clock source that can be used as an FPGA base clock.
DDC_B_Strobe* External LVDS Sample Clock source that can be used as an FPGA base clock.
*DDC_A_Strobe and DDC_B_Strobe are only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
14.1 and later FlexRIO Adapter Module Support 14.1 and later DDC_A_Strobe and DDC_B_Strobe
1.2 and earlier FlexRIO Adapter Module Support 14.0 and earlier IO Module Clock 0 and IO Module Clock 1

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