NI 6585 DDR Connector CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This double-data-rate (DDR) CLIP provides read/write access to all low-voltage differential signal (LVDS) lines on each connector, where the lines are grouped per connector and by clock edge (rising or falling). NI 6585 DDR Connector CLIP has 32 data lines, eight PFI lines, two clock input signals, two clock output signals, and allows for individual clock output inversion. In the LabVIEW FPGA Module, each connector is accessed using a U16 data type for rising edge data and a U16 data type for falling edge data.

This CLIP allows you to export a clock on each connector. LabVIEW generates this clock, which can be inverted before it is output. Inverting this clock allows you to synchronize the output data to either the rising or falling edge. Setting the invert clock signal to FALSE synchronizes to the rising edge, while setting the invert clock signal to TRUE synchronizes to a falling edge.

The following diagrams show how the NI 6585 DDR Connector CLIP routes data and clock signals.

Input/Acquisition Output/Generation



Note Note  NI 6585 DDR Connector CLIP signals are synchronous to specific clocks. In your LabVIEW FPGA VI, ensure that all Read signals are synchronized to the appropriate DDCx_AcqClock, and all Write signals are synchronized to the appropriate DDCx_GenClock.
The signals on this CLIP interface are synchronous to specific clocks. Therefore, only use them in the proper clock domain in your LV FPGA diagram.

Example Projects

FlexRIO support installation includes a variety of example projects to help get you started with the NI 6585 Basic Channel CLIP. To access these examples in NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. By default, the following example projects use the I/O signals exposed by the NI 6585 Basic Connector CLIP. To use these examples with the NI 6585 Basic Channel CLIP, right click the IO Module (NI 6585 : NI 6585 Basic Connector CLIP) item beneath your FPGA target and select Properties. In the Properties dialog, select NI 6585 Basic Channel from the Component Level IP list. The I/O defined by the NI 6585 Basic Channel CLIP automatically populates the IO Module item in the Project Explorer window.

  • NI 6585 Cont Acq with FIFO - Internal Clock.lvproj—This example performs a simple digital data acquisition from the two connectors of the NI 6585 IO Module. This example also makes use of the onboard DRAM memory banks to create a deep onboard FIFO.
  • NI 6585 Continuous Acquisition - Internal Clock.lvproj—This example performs a simple digital data acquisition from the two connectors of the NI 6585 IO Module.
  • NI 6585 Continuous Acquisition DDR - External Clock.lvproj—This example performs a simple digital data acquisition at double data rate from the two connectors of the NI 6585 IO Module.
  • NI 6585 Continuous Generation DDR - Internal Clock.lvproj—This example continuously drives data out of connectors A and B on the NI 6585.
  • NI 6585 Continuous Waveform Generation - Advanced.lvproj—This example sends two waveforms to the FPGA target via DMA FIFO to be stored into the target's DRAM. You can control the waveforms to be generated through the two connectors of the NI 6585.
  • NI 6585 Finite Acquisition and Generation - Simple.lvproj—This example generates either a digitial count or a constant value on port 0 of connector B and reads the pattern back on port 0 of connector A on the  6585.

For more information about using an example project to get started with the NI 6585, refer to the Getting Results with the NI PXI-6585R document, shipped with your device and available at ni.com/manuals.

CLIP I/O Signals

The following table describes the NI 6585 DDR Connector CLIP I/O signals:

CLIP Signal Name

(DDCA Connector; DDCB Connector)
Data Type Bit NI 6585 Connector Pin NI 6585 Connector Signal Description
DDCA_Data_Rd_Rise/DDCA_Data_Wr_Rise;

DDCB_Data_Rd_Rise/DDCB_Data_Wr_Rise
U16 0 2, 3 DIO0+, DIO0– LVDS channels for rising edge data

Each bit corresponds to a different data line. For example, bit 0 = Data_Rd_Rise0, bit 1 = Data_Rd_Rise1, and so on.
1 37, 38 DIO1+, DIO1–
2 5, 6 DIO2+, DIO2–
3 40, 41 DIO3+, DIO3–
4 8, 9 DIO4+, DIO4–
5 43, 44 DIO5+, DIO5–
6 11, 12 DIO6+, DIO6–
7 46, 47 DIO7+, DIO7–
8 14, 15 DIO8+, DIO8–
9 49, 50 DIO9+, DIO9–
10 17, 18 DIO10+, DIO10–
11 52, 53 DIO11+, DIO11–
12 20, 21 DIO12+, DIO12–
13 55, 56 DIO13+, DIO13–
14 23, 24 DIO14+, DIO14–
15 58, 59 DIO15+, DIO15–
DDCA_Data_Rd_Fall/DDCA_Data_Wr_Fall;

DDCB_Data_Rd_Fall/DDCB_Data_Wr_Fall
U16 0 2, 3 DIO0+, DIO0– LVDS channels for falling edge data

Each bit corresponds to a different data line. For example, bit 0 = Data_Rd_Fall0, bit 1 = Data_Rd_Fall1, and so on.
1 37, 38 DIO1+, DIO1–
2 5, 6 DIO2+, DIO2–
3 40, 41 DIO3+, DIO3–
4 8, 9 DIO4+, DIO4–
5 43, 44 DIO5+, DIO5–
6 11, 12 DIO6+, DIO6–
7 46, 47 DIO7+, DIO7–
8 14, 15 DIO8+, DIO8–
9 49, 50 DIO9+, DIO9–
10 17, 18 DIO10+, DIO10–
11 52, 53 DIO11+, DIO11–
12 20, 21 DIO12+, DIO12–
13 55, 56 DIO13+, DIO13–
14 23, 24 DIO14+, DIO14–
15 58, 59 DIO15+, DIO15–
DDCA_Data_WE;

DDCB_Data_WE
U16 Bitwise write enable for the data. If the bit is set (='1') then the channel is enabled. Each bit corresponds to a different data line. For example, bit 0 = Data_Wr0, bit 1 = Data_Wr1, and so on.
DDCA_PFI_Rd_Rise/DDCA_PFI_Wr_Rise;

DDCB_PFI_Rd_Rise/DDCB_PFI_Wr_Rise
U8 1 29, 30 PFI 1+, PFI 1– LVDS channels for rising edge data. Unspecified bits are ignored, for example, bit 0 is disregarded by this signal.
2 64, 65 PFI 2+, PFI 2–
3 32, 33 PFI 3+, PFI 3–
4 67, 68 PFI 4+, PFI 4–
DDCA_PFI_Rd_Fall/DDCA_PFI_Wr_Fall;

DDCB_PFI_Rd_Fall/DDCB_PFI_Wr_Fall
U8 1 29, 30 PFI 1+, PFI 1– LVDS channels for falling edge data. Unspecified bits are ignored, for example, bit 0 is disregarded by this signal.
2 64, 65 PFI 2+, PFI 2–
3 32, 33 PFI 3+, PFI 3–
4 67, 68 PFI 4+, PFI 4–
DDCA_PFI_WE;

DDCB_PFI_WE
U8 Bitwise write enable for the data. If the bit is set (='1') then the channel is enabled. Each bit corresponds to a different data line. For example, bit 1 = PFI_Wr1, bit 2 = PFI_Wr2, and so on. Unspecified bits are ignored, for example, bit 0 is disregarded by this signal.
DDCA_GenClock;

DDCB_GenClock
Bool 61, 62 PFI 0+, PFI 0– Clock to export on the Clock Out/PFI 0 line. This is also the input clock for the output DDR flip-flops.
Caution Caution  All Write, Write Enable, Clock Out Enable, and Clock Out Invert signals must be accessed from the GenClock clock domain. Accessing these signals from other clock domains can result in undesired behaviors such as samples being omitted or output multiple times. The VI will not compile until these signals are accessed from the correct clock domain.
DDCA_ClockOut_En;

DDCB_ClockOut_En
Bool Output enable for Clock Out/PFI 0.

TRUE = Enabled

FALSE = Disabled
DDCA_ClockOut_Invert;

DDCB_ClockOut_Invert
Bool This signal controls the 180° phase shift of the output clock.

FALSE = No shift

TRUE = 180° shift (invert)
DDCA_AcqClock;

DDCB_AcqClock
Bool Input clock for the input DDR flip-flops.
Caution Caution  All Read signals must be accessed from the AcqClock clock domain. Accessing these signals from other clock domains can result in undesired behaviors such as samples being lost or read multiple times. The VI will not compile until these signals are accessed from the correct clock domain.
IO Module Clock 0 Bool 26, 27 (on DDCA connector) GLOBAL CLK 0+,

GLOBAL CLK 0–
External Sample Clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties dialog box and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
IO Module Clock 1 Bool 26, 27 (on DDCB connector) GLOBAL CLK 1+,

GLOBAL CLK 1–
External Sample Clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties dialog box and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.

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