NI 6589 Component-Level IP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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The FlexRIO Adapter Module Support software comes with component-level IP (CLIP) options that provide access to the NI 6589 physical I/O from within the LabVIEW FPGA environment.

In the IO Module Properties dialog box, select National Instruments: NI 6589 from the IO Modules list in the General category. The compatible CLIP items are automatically displayed in the Component Level IP window.

To use a CLIP item with your LabVIEW project, select the CLIP item in the Component Level IP window and select OK. The I/O defined by the selected CLIP automatically populates the IO Module item in the Project Explorer window.

The following NI-developed CLIP options are compatible with the NI 6589.

CLIP NameCLIP Description
NI 6589 Basic ConnectorThis CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels, where the channels are grouped by connector. This CLIP has 16 bidirectional data LVDS lines, four LVDS PFI lines, one LVDS STROBE line, one LVDS clock output signal, four single-ended PFI lines, and one single-ended clock input signal, and the CLIP allows for individual clock output inversion. You can access the LVDS data and direction lines using a U16 data type in which each bit position corresponds to an individual channel. You can access the LVDS PFI lines and the single-ended PFI lines using a Boolean control.
NI 6589 Serdes ChannelThis CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels using a channel-based interface. This CLIP has 16 bidirectional data LVDS lines, four LVDS PFI lines, one LVDS STROBE line, one LVDS clock output signal, four single-ended PFI lines, and one single-ended clock input signal, and the CLIP allows for individual clock output inversion.

You can access each of the LVDS data and PFI channels using a U16 data type in which the top six bits are unused. Each LVDS line, PFI line, and clock output is connected to an OSERDES or ISERDES block that serializes or deserializes, respectively, the signal by a factor of ten by default. During acquisition, the first bit you receive is bit 9, and the last bit you receive is bit 0. During generation, the first bit you send is bit 9, and the last bit you send is bit 0. Therefore, with every regional clock cycle, the NI 6589 reads or writes ten bits of data per channel to or from the ISERDES or OSERDES blocks. All OSERDES and ISERDES blocks are set to double data rate (DDR) mode.

This CLIP is compatible only with LabVIEW 2010 and later.
NI 6589 Serdes ConnectorThis CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels, where the channels are grouped by connector. This CLIP has 16 bidirectional LVDS lines, four LVDS PFI lines, one LVDS STROBE line, one LVDS clock output signal, four single-ended PFI lines, and one single-ended clock input signal, and the CLIP allows for individual clock output inversion. This CLIP is designed to convey parallel data at high speeds.

You can access the LVDS data and direction lines using a U16 data type, you can access the LVDS PFI lines using a U8 data type, and you can access the single-ended PFI lines using a Boolean control. In the U8 data type, the top four bits are unused. Each LVDS line, PFI line, and clock output is connected to an OSERDES or ISERDES block that serializes or deserializes, respectively, the signal by a factor of six by default. Therefore, with every regional clock cycle, the NI 6589 reads or writes six samples to or from the ISERDES or OSERDES blocks. All OSERDES and ISERDES blocks are set to double data rate (DDR) mode.

This CLIP is compatible only with LabVIEW 2010 and later.
Caution  You can create custom CLIP items for the NI 6589. If you choose to develop a custom CLIP item for your application, NI recommends using one of the provided NI 6589 CLIP items as a template while referring to the NI 6589 Specifications to ensure that the proper electrical characteristics are maintained. Failure to adhere to the specified electrical requirements and signal directions may result in device damage. National Instruments is not liable for any damage resulting from such misuse. All CLIP items include logic for voltage and direction control. Use of these modules is strongly encouraged to prevent damage to the FPGA or the NI 6589.

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