NI 6589 Basic Connector CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels, where the channels are grouped by connector. This CLIP has 16 bidirectional data LVDS lines, four LVDS PFI lines, one LVDS STROBE line, one LVDS clock output signal, four single-ended PFI lines, and one single-ended clock input signal, and the CLIP allows for individual clock output inversion. You can access the LVDS data and direction lines using a U16 data type in which each bit position corresponds to an individual channel. You can access the LVDS PFI lines and the single-ended PFI lines using a Boolean control.

Note Note  The LabVIEW FPGA Module treats NI 6589 Basic Connector CLIP signals as asynchronous by inserting synchronization registers by default.

The following diagrams show how the NI 6589 Basic Connector CLIP routes data and clock signals in the FPGA.

Example Projects

FlexRIO support installation includes a variety of example projects to help get you started with the NI 6589 Basic Connector CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example project uses the I/O signals exposed by the NI 6589 Basic Connector CLIP:

  • NI 6589 Continuous Generation - Export Clock.lvproj—This example continuously generates data on all 16 data channels of the DDC connector on the NI 6589, with data rates up to 1 Gb/s per channel (exported Sample Clock up to 500 MHz).
  • NI 6589 Finite Acquisition - External Clock Start Trigger.lvproj—This example performs a finite data acquisition on 16 channels, with data rates up to 1 Gbs/s per channel, with an external clock and a pattern match start trigger. The external clock supplied on the Strobe pin determines the sample rate of the acquisition (up to 500 MHz DDR).
  • NI 6589 Finite Generation and Acquisition - Simple.lvproj—This example demonstrates how to generate and acquire data on up to eight channels using an NI 6589. The example generates either a constant value or a digital count-up pattern on the first eight even, odd, upper, or lower numbered channels of the DDC connector, and then acquires that pattern on the first eight odd, even, lower, or upper (respectively) numbered channels of the DDC connector.
  • NI 6589 Serial Acquisition - Configuration.lvproj—This FPGA VI acquires serial data on one channel, with data rates up to 1 Gb/s. The VI allows you to configure multiple settings, such as the Clock Source, Bit Slip, and data delay.
  • NI 6589 Serial Generation - Export Clock.lvproj—This example continuously generates data on one data channel, with data rates up to 1 Gb/s. The Sample Clock is exported on the LVDS Clock Out pin (exported Sample Clock up to 500 MHz). The generated data pattern is selectable as either a Static or a Count Up pattern.

For more information about the NI 6589, refer to the NI 6589 Getting Started Guide and the NI 6589 Specifications, shipped with your device and available at ni.com/manuals.

NI 6589 CLIP I/O Signals

The following table describes the NI 6589 Basic Connector CLIP I/O signals.

CLIP Signal Name Data Type NI 6589 Connector Signal Description
LVDS_Data_Dir U16 DIO <0..15>+, DIO <0..15>– LVDS direction control. Write only.

0 = I/O acquires
1 = I/O generates

The least significant bit (LSB) of the U16 corresponds with DIO 0.
LVDS_Data_Rd U16 DIO <0..15>+, DIO <0..15>– LVDS acquisition. Read only.

The least significant bit (LSB) of the U16 corresponds with DIO 0.
LVDS_Data_Wr U16 DIO <0..15>+, DIO <0..15>– LVDS generation. Write only.

The least significant bit (LSB) of the U16 corresponds with DIO 0.
LVDS_PFI_Dir Bool PFI <1..4>+, PFI <1..4>– Direction control. Write only.

TRUE = Generation
FALSE = Acquisition
LVDS_PFI_Rd Bool PFI <1..4>+, PFI <1..4>– LVDS acquisition channel. Read only.
LVDS_PFI_Wr Bool PFI <1..4>+, PFI <1..4>– LVDS generation channel. Write only.
SE_PFI0_WE Bool PFI 0 Single-ended generation PFI write enable. Write only.

TRUE = Enable
FALSE = Disable
SE_PFI1_WE SE_PFI_1
SE_PFI2_WE SE_PFI_2
SE_PFI3_WE SE_PFI_3
SE_PFI0_Rd PFI 0 Single-ended acquisition channel. Read only.
SE_PFI1_Rd SE_PFI_1
SE_PFI2_Rd SE_PFI_2
SE_PFI3_Rd SE_PFI_3
SE_PFI0_Wr PFI 0 Single-ended generation channel. Write only.
SE_PFI1_Wr SE_PFI_1
SE_PFI2_Wr SE_PFI_2
SE_PFI3_Wr SE_PFI_3
LVDS_ClockOut_Enable Bool DDC CLK OUT+, DDC CLK OUT– Exported LVDS clock enable. Write only.

TRUE = Enabled
FALSE = Disabled
LVDS_ClockOut_Invert Bool DDC CLK OUT+, DDC CLK OUT– Exported LVDS clock polarity control. Write only.

TRUE = Inverted
FALSE = Noninverted
Onboard_Clock_Write_Data U16 Registers address and data to be written to the onboard clock chip. The top eight bits contain the address, and the bottom eight bits contain the data.
Onboard_Clock_Write Bool Latches the value of Onboard_Clock_Write_Data on a rising edge transition. Write only.
Onboard_Clock_Ready Bool Indicates when the onboard clock is ready for new write commands. Read only.
IO_Module_Clock_1_Source U8 Selects the global clock source from the crosspoint switch. Write only.

0 = Tristate—Output disabled (high impedance).
2 = DStarA (PXIe Only)—Clock from PXI Express backplane.
3 = Adapter Module Onboard Clock—Clock generated from the Si570 clock chip.
4 = Strobe From Crosspoint Switch—LVDS STROBE from crosspoint switch.

Note Note  For more information about the crosspoint switch, refer to the NI 6589 Getting Started Guide.
Xpoint_Switch_Write Bool Latches the clock source selection onto the crosspoint switch on a rising edge transition. Write only.
Xpoint_Switch_Ready Bool Indicates when the crosspoint switch is ready for new write commands. Read only.
Onboard_Clock_Configuration_Clock Bool Clock used to control the crosspoint switch and the adapter module onboard clock state machines. This clock must be connected to a 40 MHz onboard clock.
Single Ended Global Clock Bool External single-ended Sample Clock source that can be used as an FPGA base clock.
LVDS Global Clock Bool External LVDS Sample Clock source that can be used as an FPGA base clock. This clock is routed from the crosspoint switch directly to a global clock buffer (BUFG). It has the same clock rate as the IO_Module_Clock_1_Source signal.
LVDS_ClockOut Bool DDC CLK OUT+, DDC CLK OUT– Exported LVDS clock. You can select the source for this clock in the Clock Selections category of the IO Module Properties dialog box. Write only.

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