NI 6589 Serdes Channel CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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Note Note  This CLIP is compatible only with LabVIEW 2010 and later.

This CLIP provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels using a channel-based interface. This CLIP has 16 bidirectional data LVDS lines, four LVDS PFI lines, one LVDS STROBE line, one LVDS clock output signal, four single-ended PFI lines, and one single-ended clock input signal, and the CLIP allows for individual clock output inversion.

You can access each of the LVDS data and PFI channels using a U16 data type in which the top six bits are unused. Each LVDS line, PFI line, and clock output is connected to an OSERDES or ISERDES block that serializes or deserializes, respectively, the signal by a factor of ten by default. During acquisition, the first bit you receive is bit 9, and the last bit you receive is bit 0. During generation, the first bit you send is bit 9, and the last bit you send is bit 0. Therefore, with every regional clock cycle, the NI 6589 reads or writes ten bits of data per channel to or from the ISERDES or OSERDES blocks. All OSERDES and ISERDES blocks are set to double data rate (DDR) mode.

Acquisition and generation channels are clocked by the Acq_Regional_Clock and Gen_Regional_Clock signals, respectively. The PFI acquisition and generation channels are clocked by the PFI_Regional_Clock signal. The regional clocks are generated by regional clock buffers (BUFR), which divide the selected IO Clock Source signal. You can select the IO Clock Source signal by configuring the crosspoint switch. By default, the value of a regional clock in this CLIP is equal to the value of the respective IO Clock Source signal divided by five.

Acquisition channels are connected to IDELAY blocks, which allow for per channel data delay. Each Chx_Idelay_Increment and PFIx_Idelay_Increment signal corresponds to its respective channel. A logic high level increases the data delay by one tap per Acq_Regional_Clock cycle or PFI_Regional_Clock cycle. In this CLIP, a tap is equal, nominally, to 78.125 picoseconds when the IDelay_Calibration_Clock signal is set to 200 MHz. For more information about IDELAY and taps, refer to Chapter 7: SelectIO Logic Resources in the Virtex-5 FPGA User Guide available at www.xilinx.com.

During acquisition, you can configure the bit order of the deserialized data by using the Chx_Bitslip and PFIx_Bitslip signals. Each Chx_Bitslip and PFIx_Bitslip signal corresponds to its respective channel. A logic high level causes the bit order to shift once per Acq_Regional_Clock cycle or PFI_Regional_Clock cycle. For more information about bitslip operations, refer to Chapter 8: Advanced SelectIO Logic Resources in the Virtex-5 FPGA User Guide, available at www.xilinx.com.

Block Diagrams

Input/Acquisition

The following diagram shows how the NI 6589 Serdes Channel CLIP routes data and clock signals in the FPGA during acquisition.

Output/Generation

The following diagram shows how the NI 6589 Serdes Channel CLIP routes data and clock signals in the FPGA during generation.

PFI

The following diagram shows how the NI 6589 Serdes Channel CLIP routes PFI signals in the FPGA during acquisition and generation.

Timing Diagrams

Note Note  The following acquisition and generation timing diagrams are also applicable for the LVDS PFI signals.

Input/Acquisition

The following timing diagram shows how serial data is acquired with the NI 6589 Serdes Channel CLIP.

Note Note  For more information about bitslip operations, refer to Chapter 8: Advanced SelectIO Logic Resources in the Virtex-5 FPGA User Guide, available at www.xilinx.com.

Output/Generation

The following timing diagram shows how parallel data is generated with the NI 6589 Serdes Channel CLIP.

Note Note  The above diagram assumes that there are no synchronization registers on the LVDS_Chx_Wr port. For more information about the output latencies of the OSERDES blocks, refer to Chapter 8: Advanced SelectIO Logic Resources in the Virtex-5 FPGA User Guide, available at www.xilinx.com.

Example Projects

FlexRIO support installation includes a variety of example projects to help get you started with the NI 6589 Basic Connector CLIP. To access these examples using the NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules. The following example project uses the I/O signals exposed by the NI 6589 Basic Connector CLIP:

  • NI 6589 Continuous Generation - Export Clock.lvproj—This example continuously generates data on all 16 data channels of the DDC connector on the NI 6589, with data rates up to 1 Gb/s per channel (exported Sample Clock up to 500 MHz).
  • NI 6589 Finite Acquisition - External Clock Start Trigger.lvproj—This example performs a finite data acquisition on 16 channels, with data rates up to 1 Gbs/s per channel, with an external clock and a pattern match start trigger. The external clock supplied on the Strobe pin determines the sample rate of the acquisition (up to 500 MHz DDR).
  • NI 6589 Finite Generation and Acquisition - Simple.lvproj—This example demonstrates how to generate and acquire data on up to eight channels using an NI 6589. The example generates either a constant value or a digital count-up pattern on the first eight even, odd, upper, or lower numbered channels of the DDC connector, and then acquires that pattern on the first eight odd, even, lower, or upper (respectively) numbered channels of the DDC connector.
  • NI 6589 Serial Acquisition - Configuration.lvproj—This FPGA VI acquires serial data on one channel, with data rates up to 1 Gb/s. The VI allows you to configure multiple settings, such as the Clock Source, Bit Slip, and data delay.
  • NI 6589 Serial Generation - Export Clock.lvproj—This example continuously generates data on one data channel, with data rates up to 1 Gb/s. The Sample Clock is exported on the LVDS Clock Out pin (exported Sample Clock up to 500 MHz). The generated data pattern is selectable as either a Static or a Count Up pattern.

For more information about the NI 6589, refer to the NI 6589 Specifications and the NI 6589 Getting Started Guide, shipped with your device and available at ni.com/manuals.

NI 6589 CLIP I/O Signals

The following table describes the NI 6589 Channel SERDES CLIP I/O signals.

CLIP Signal Name Data Type NI 6589 Connector Signal Description
Acq_Reset Bool When asserted, this signal resets any FPGA circuitry clocked by the Acq_Regional_Clock. Use this signal when the Acq_IO_Clock_Source has been reconfigured.
Gen_Reset Bool When asserted, this signal resets any FPGA circuitry clocked by the Gen_Regional_Clock. Use this signal when the Gen_IO_Clock_Source has been reconfigured.
PFI_Reset Bool When asserted, this signal resets any FPGA circuitry clocked by the PFI_Regional_Clock. Use this signal when the PFI_IO_Clock_Source has been reconfigured.
LVDS_Data_Dir U16 DIO <0..15>+, DIO <0..15>– LVDS direction control. Write only.

0 = I/O acquires
1 = I/O generates

The least significant bit (LSB) of the U16 corresponds with DIO 0
LVDS_Ch0_Rd U16 DIO 0+, DIO 0– LVDS acquisition channel. Read only. Bit 9 is acquired first. The top six bits are unused.
LVDS_Ch1_Rd DIO 1+, DIO 1–
LVDS_Ch2_Rd DIO 2+, DIO 2–
LVDS_Ch3_Rd DIO 3+, DIO 3–
LVDS_Ch4_Rd DIO 4+, DIO 4–
LVDS_Ch5_Rd DIO 5+, DIO 5–
LVDS_Ch6_Rd DIO 6+, DIO 6–
LVDS_Ch7_Rd DIO 7+, DIO 7–
LVDS_Ch8_Rd DIO 8+, DIO 8–
LVDS_Ch9_Rd DIO 9+, DIO 9–
LVDS_Ch10_Rd DIO 10+, DIO 10–
LVDS_Ch11_Rd DIO 11+, DIO 11–
LVDS_Ch12_Rd DIO 12+, DIO 12–
LVDS_Ch13_Rd DIO 13+, DIO 13–
LVDS_Ch14_Rd DIO 14+, DIO 14–
LVDS_Ch15_Rd DIO 15+, DIO 15–
Ch0_Bitslip Bool DIO 0+, DIO 0– Reorders the parallel output of the ISERDES module. A logic high level causes the bit order to shift once per Acq_Regional_Clock cycle or PFI_Regional_Clock cycle.
Ch1_Bitslip DIO 1+, DIO 1–
Ch2_Bitslip DIO 2+, DIO 2–
Ch3_Bitslip DIO 3+, DIO 3–
Ch4_Bitslip DIO 4+, DIO 4–
Ch5_Bitslip DIO 5+, DIO 5–
Ch6_Bitslip DIO 6+, DIO 6–
Ch7_Bitslip DIO 7+, DIO 7–
Ch8_Bitslip DIO 8+, DIO 8–
Ch9_Bitslip DIO 9+, DIO 9–
Ch10_Bitslip DIO 10+, DIO 10–
Ch11_Bitslip DIO 11+, DIO 11–
Ch12_Bitslip DIO 12+, DIO 12–
Ch13_Bitslip DIO 13+, DIO 13–
Ch14_Bitslip DIO 14+, DIO 14–
Ch15_Bitslip DIO 15+, DIO 15–
Ch0_Idelay_Increment Bool DIO 0+, DIO 0– Adds delay to the acquired data. A logic high level increases the data delay by one tap per Acq_Regional_Clock cycle or PFI_Regional_Clock cycle. In this CLIP, a tap is equal, nominally, to 78.125 picoseconds when the IDelay_Calibration_Clock signal is set to 200 MHz.
Ch1_Idelay_Increment DIO 1+, DIO 1–
Ch2_Idelay_Increment DIO 2+, DIO 2–
Ch3_Idelay_Increment DIO 3+, DIO 3–
Ch4_Idelay_Increment DIO 4+, DIO 4–
Ch5_Idelay_Increment DIO 5+, DIO 5–
Ch6_Idelay_Increment DIO 6+, DIO 6–
Ch7_Idelay_Increment DIO 7+, DIO 7–
Ch8_Idelay_Increment DIO 8+, DIO 8–
Ch9_Idelay_Increment DIO 9+, DIO 9–
Ch10_Idelay_Increment DIO 10+, DIO 10–
Ch11_Idelay_Increment DIO 11+, DIO 11–
Ch12_Idelay_Increment DIO 12+, DIO 12–
Ch13_Idelay_Increment DIO 13+, DIO 13–
Ch14_Idelay_Increment DIO 14+, DIO 14–
Ch15_Idelay_Increment DIO 15+, DIO 15–
LVDS_Ch0_Wr U16 DIO 0+, DIO 0– LVDS generation channel. Write only. Bit 9 is generated first. The top six bits are unused.
LVDS_Ch1_Wr DIO 1+, DIO 1–
LVDS_Ch2_Wr DIO 2+, DIO 2–
LVDS_Ch3_Wr DIO 3+, DIO 3–
LVDS_Ch4_Wr DIO 4+, DIO 4–
LVDS_Ch5_Wr DIO 5+, DIO 5–
LVDS_Ch6_Wr DIO 6+, DIO 6–
LVDS_Ch7_Wr DIO 7+, DIO 7–
LVDS_Ch8_Wr DIO 8+, DIO 8–
LVDS_Ch9_Wr DIO 9+, DIO 9–
LVDS_Ch10_Wr DIO 10+, DIO 10–
LVDS_Ch11_Wr DIO 11+, DIO 11–
LVDS_Ch12_Wr DIO 12+, DIO 12–
LVDS_Ch13_Wr DIO 13+, DIO 13–
LVDS_Ch14_Wr DIO 14+, DIO 14–
LVDS_Ch15_Wr DIO 15+, DIO 15–
LVDS_PFI_Dir U8 PFI <1..4>+, PFI <1..4>– Direction control. Write only.

TRUE = Generation
FALSE = Acquisition

The LSB of the U8 corresponds with PFI 1. The top four bits are unused.
LVDS_PFI1_Rd U16 PFI 1+, PFI 1– LVDS acquisition channel. Read only. Bit 9 is acquired first. The top six bits are unused.
LVDS_PFI2_Rd U16 PFI 2+, PFI 2–
LVDS_PFI3_Rd U16 PFI 3+, PFI 3–
LVDS_PFI4_Rd U16 PFI 4+, PFI 4–
PFI1_Bitslip Bool PFI 1+, PFI 1– Reorders the parallel output of the ISERDES module. A logic high level causes the bit order to shift once per Acq_Regional_Clock cycle or PFI_Regional_Clock cycle.
PFI2_Bitslip PFI 2+, PFI 2–
PFI3_Bitslip PFI 3+, PFI 3–
PFI4_Bitslip PFI 4+, PFI 4–
PFI1_Idelay_Increment Bool PFI 1+, PFI 1– Adds delay to the acquired data. A logic high level increases the data delay by one tap per Acq_Regional_Clock cycle or PFI_Regional_Clock cycle. In this CLIP, a tap is equal, nominally, to 78.125 picoseconds when the IDelay_Calibration_Clock signal is set to 200 MHz.
PFI2_Idelay_Increment PFI 2+, PFI 2–
PFI3_Idelay_Increment PFI 3+, PFI 3–
PFI4_Idelay_Increment PFI 4+, PFI 4–
LVDS_PFI1_Wr U16 PFI 1+, PFI 1– LVDS generation channel. Write only. Bit 9 is generated first. The top six bits are unused.
LVDS_PFI2_Wr PFI 2+, PFI 2–
LVDS_PFI3_Wr PFI 3+, PFI 3–
LVDS_PFI4_Wr PFI 4+, PFI 4–
SE_PFI0_WE Bool PFI 0 Single-ended generation PFI write enable. Write only.

TRUE = Enable
FALSE = Disable
SE_PFI1_WE SE_PFI_1
SE_PFI2_WE SE_PFI_2
SE_PFI3_WE SE_PFI_3
SE_PFI0_Rd Bool PFI 0 Single-ended acquisition channel. Read only.
SE_PFI1_Rd SE_PFI_1
SE_PFI2_Rd SE_PFI_2
SE_PFI3_Rd SE_PFI_3
SE_PFI0_Wr Bool PFI 0 Single-ended generation channel. Write only.
SE_PFI1_Wr SE_PFI_1
SE_PFI2_Wr SE_PFI_2
SE_PFI3_Wr SE_PFI_3
LVDS_ClockOut_Enable Bool DDC CLK OUT+, DDC CLK OUT– Exported LVDS clock enable. Write only.

TRUE = Enabled
FALSE = Disabled
LVDS_ClockOut_Invert Bool DDC CLK OUT+, DDC CLK OUT– Exported LVDS clock polarity control. Write only.

TRUE = Inverted
FALSE = Noninverted
Onboard_Clock_Write_Data U16 Registers address and data to be written to the onboard clock chip. The top eight bits contain the address, and the bottom eight bits contain the data.
Onboard_Clock_Write Bool Latches the value of Onboard_Clock_Write_Data on a rising edge transition. Write only.
Onboard_Clock_Ready Bool Indicates when the onboard clock is ready for new write commands. Read only.
Acq_IO_Clock_Source U8 Selects the acquisition I/O clock source from the crosspoint switch. Write only.

0 = Tristate—Output disabled (high impedance).
2 = DStarA (PXIe Only)—Clock from PXI Express backplane.
3 = Adapter Module Onboard Clock—Clock generated from the Si570 clock chip.
4 = Strobe From Crosspoint Switch—LVDS STROBE from crosspoint switch.
5 = Strobe Bypass—LVDS STROBE bypasses the crosspoint switch. The propagation delay of the Strobe Bypass exactly matches the propagation delay of the data channels.

Note Note  For more information about the crosspoint switch, refer to the NI 6589R Getting Started Guide.
PFI_IO_Clock_Source U8 Selects the PFI I/O clock source from the crosspoint switch. Write only.

0 = Tristate—Output disabled (high impedance).
2 = DStarA (PXIe Only)—Clock from the PXI Express backplane.
3 = Adapter Module Onboard Clock—Clock generated from the Si570 clock chip.
4 = Strobe From Crosspoint Switch—LVDS STROBE from crosspoint switch.

If Acq_IO_Clock_Source is set to Strobe Bypass, this signal cannot be set to Strobe From Crosspoint Switch.

Note Note  For more information about the crosspoint switch, refer to the NI 6589R Getting Started Guide.
Gen_IO_Clock_Source U8 Selects the generation I/O clock source from the crosspoint switch. Write only.

0 = Tristate—Output disabled (high impedance).
2 = DStarA (PXIe Only)—Clock from PXI Express backplane.
3 = Adapter Module Onboard Clock—Clock generated from the Si570 clock chip.
4 = Strobe From Crosspoint Switch—LVDS STROBE from crosspoint switch.

If Acq_IO_Clock_Source is set to Strobe Bypass, this signal cannot be set to Strobe From Crosspoint Switch.

Note Note  For more information about the crosspoint switch, refer to the NI 6589R Getting Started Guide.
IO_Module_Clock_1_Source U8 Selects the global clock source from the crosspoint switch. Write only.

0 = Tristate—Output disabled (high impedance).
2 = DStarA (PXIe Only)—Clock from PXI Express backplane.
3 = Adapter Module Onboard Clock—Clock generated from the Si570 clock chip.
4 = Strobe From Crosspoint Switch—LVDS STROBE from crosspoint switch.

If Acq_IO_Clock_Source is set to Strobe Bypass, this signal cannot be set to Strobe From Crosspoint Switch.

Note Note  For more information about the crosspoint switch, refer to the NI 6589R Getting Started Guide.
Xpoint_Switch_Write Bool Latches the clock source selection onto the crosspoint switch on a rising edge transition. Write only.
Xpoint_Switch_Ready Bool Indicates when the crosspoint switch is ready for new write commands. Read only.
Acq_Regional_Clock Bool Receives parallel data from ISERDES modules for acquisition data channels. The value of this clock is equal to the value of Acq_IO_Clock_Source clock divided by 5.
Gen_Regional_Clock Bool Sends parallel data to OSERDES modules for generation data channels. The value of this clock is equal to the value of Gen_IO_Clock_Source clock divided by 5.
PFI_Regional_Clock Bool Conveys parallel data to and from OSERDES and ISERDES modules for PFI channels. The value of this clock is equal to the value of PFI_IO_Clock_Source clock divided by 5.
LVDS_ClockOut Bool DDC CLK OUT+, DDC CLK OUT– Exported LVDS clock. This clock is sourced by the PFI_IO_Clock_Source signal.
IDelay_Calibration_Clock Bool Clock used to calibrate the IDELAY blocks which determine the resolution of a single IDELAY tap.
Onboard_Clock_Configuration_Clock Bool Clock used to control the crosspoint switch and the adapter module onboard clock state machines. This clock must be connected to a 40 MHz onboard clock.
Single Ended Global Clock Bool External single-ended Sample Clock source that can be used as an FPGA base clock.
LVDS Global Clock Bool External LVDS Sample Clock source that can be used as an FPGA base clock. This clock is routed from the crosspoint switch directly to a global clock buffer (BUFG). It has the same clock rate as the IO_Module_Clock_1_Source signal.

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