NI 1483 CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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The following table describes the NI 1483 CLIP I/O signals.

CLIP Signal Name Data Type Read/Write Description
Clocks
Clock 40 MHz Clock N/A This clock must be connected to the 40 MHz Onboard Clock using the Clock Selections option in the IO Modules Properties dialog. No other clock frequency may be used. The Camera Link UART signals must be read and written synchronously to this clock.
Image Data Clock Clock N/A This clock must be connected to a clock that is faster than the connected camera's maximum clock rate using the Clock Selections option in the IO Modules Properties dialog. For example, a 100 MHz clock may generally be used since it is faster than the maximum supported Camera Link clock frequency of 85 MHz. Slower clocks may be used as long as the clock's frequency is faster than that of the camera.

Camera Link Data signals must be read synchronously to this clock.

Configuration Signals
Configuration Signals must be set before initializing an acquisition. They must be set using constants in the target FPGA VI before the acquisition initialization, or using controls in the target FPGA VI that are set by the host VI before the FPGA VI is run.
CL Set Signal Mapping U8 Write Sets the signal mapping to use for the Camera Link connectors:
  • 0 = Standard Camera Link
  • 1 = Basler 10-tap
  • 2 = Vossküler 10-tap

If not driven, CL Set Signal Mapping defaults to 0 (Standard Camera Link).

CL Set Configuration U8 Write Sets the Camera Link configuration:
  • 0 = Base
  • 1 = Medium
  • 2 = Full/Extended/10-tap

If not driven, CL Set Configuration defaults to 0 (Base).

CL Set FVAL Active High

CL Set LVAL Active High

CL Set DVAL Active High

CL Set Spare Active High

Boolean Write These signals set the polarity for the indicated Camera Link flag.
  • TRUE = Active high (high true)
  • FALSE = Active low (low true)

If not driven, CL Active High signals default to TRUE.

CL Set Line Scan Boolean Write When this signal is TRUE, the initialization circuitry does not require a Camera Link FVAL signal to complete initialization. Set to TRUE for a line scan camera. Set to FALSE for an area scan camera. If not driven, CL Set Linescan defaults to FALSE.
Acquisition Initialization
CL Acq Init Boolean Write This input signal initializes the Camera Link front end. This allows the front end to detect and synchronize with the Camera Link signals from the camera. Initialize this signal to FALSE at the start of your application. The procedure for initialization is as follows:
  1. Set the signal mapping, configuration, line scan mode, and flags polarity before running the FPGA, as described above
  2. After the FPGA has started, set the CL Acq Init signal to the TRUE
  3. Wait until the CL Acq Ready signal becomes TRUE
  4. Return the CL Acq Init signal to FALSE

Once initialization is complete, you can begin to monitor the Camera Link data and flags signals.

CL Acq Ready Boolean Read This output signal indicates when the acquisition initialization has completed and a valid camera source has been detected. If this signal never becomes TRUE, then a valid Camera Link signal could not be detected.
Camera Link Data
Camera Link Data signals must be used within single-cycle timed loop running on the Image Data Clock.

CL Port A

CL Port B

...

CL Port J

U8 Read Camera Link data output ports. All image data is output on one or more of these ten ports using the Image Data Clock. These ports should be ignored during clock cycles in which CL Output Valid is false.

CL Frame Valid

CL Line Valid

CL Data Valid

CL Spare

Boolean Read Camera Link enable flags. These signals are always output active high (high true). The enable signals should be ignored during clock cycles in which CL Output Valid is false.
CL Output Valid Boolean Read Indicates whether or not the CL Port and CL Valid signals have active data. Because the Image Data Clock is faster than the camera's pixel clock (maximum of 85 MHz), there will be clock cycles in which the Camera Link front end has no data or flags to output. The CL Output Valid will be TRUE for clock cycles that have valid data and/or flags and FALSE during clock cycles that do not. The output of the CL Port and Valid signals should be ignored whenever CL Output Valid is FALSE.
Camera Control Lines

CL Control 1

CL Control 2

CL Control 3

CL Control 4

Boolean Write When CL Control Enable is TRUE, these signals drive the four camera control signals on the Camera Link cable.
Cl Control Enable Boolean Write This signal controls whether the camera control lines on the Camera Link cable are driven by the CL Control signals.
  • TRUE = Enabled (driving)
  • FALSE = Disabled (high impedance)
I/O Lines

TTL In 0

TTL In 1

TTL In 2

TTL In 3

Boolean Read These signals indicate the state of the TTL IO lines. To use a TTL IO signal as an input, the corresponding TTL Out Enable signal must be set to FALSE.

TTL Out 0

TTL Out 1

TTL Out 2

TTL Out 3

Boolean Write These signals set the state of the TTL IO lines. To use a TTL IO signal as an output, the corresponding TTL Out Enable signal must be set to TRUE.

ISO In 0

ISO In 1

Boolean Read These signals indicate the state of the isolated input lines.

ISO Out 0

ISO Out 1

Boolean Write These signals indicate the state of the isolated output lines.

QE Phase A

QE Phase B

Boolean Read These signals indicate the state of the quadrature encoder phase A and phase B inputs.
Camera Link Serial Interface (UART)
Camera Link Serial Interface (UART) signals must be used within a single-cycle timed loop running on the same 40 MHz clock that is assigned to Clock 40 MHz in the IO Module Properties dialog box.
UART Set Baud Rate Boolean Write This signal is used to set the baud rate of the Camera Link serial interface. The procedure for setting the baud rate is as follows:
  1. Set the UART Baud Rate In signal to the code for the desired baud rate.
  2. Set the UART Set Baud Rate signal to TRUE.
  3. Wait until the UART Set Baud Rate Ack signal becomes TRUE.
  4. Set the UART Set Baud Rate signal to FALSE.
  5. Wait until the UART Set Baud Rate Ack signal becomes FALSE.
UART Set Baud Rate Ack Boolean Read This signal acknowledges when the setting of the baud rate has completed.
UART Baud Rate In U8 Write This signal is used to set which baud rate to use. It can be any of the standard Camera Link baud rates, as shown below:
  • 1 = 9,600 baud
  • 2 = 19,200 baud
  • 4 = 38,400 baud
  • 8 = 57,600 baud
  • 16 = 115,200 baud
  • 32 = 230,400 baud
  • 64 = 460,800 baud
  • 128 = 921,600 baud
UART RX Ready Boolean Read Indicates that the UART has received data that is ready to be read.
UART Read Enable Boolean Write This signal is used to read a received byte from the UART. When the UART RX Ready signal is TRUE, set this signal to TRUE for exactly two clock cycles then set it to FALSE for at least one clock cycle to perform the read. The byte will be output on the UART Read Data signal.
UART Read Data U8 Read This signal provides the data byte that was received from the camera. The data on this signal is valid during the second cycle of the two-cycle assertion of the UART Read Enable signal. This signal does not have valid data before the read enable is asserted or after read enable is de-asserted.
UART TX Ready Boolean Read Indicates that the UART is ready to accept a new byte to transmit to the camera.
UART Write Data U8 Write Set this signal to the data value to be written to the camera over the serial interface.
UART Write Enable Boolean Write This signal is used to write a byte to the UART for transmission to the camera. When you have a byte to send, write the data to UART Write Data then set this signal to TRUE for exactly one clock cycle. This signal is ignored unless UART TX Ready is TRUE.
UART Break Indicator Boolean Read This signal indicates that the received byte being output on UART Read Data was received as part of a break condition. A break condition occurs when the RX serial input signal is held low by the camera for longer than the time required to send a full byte. In this case, the data byte received has the value 0 and the UART Break Indicator will be TRUE when the byte is read.
UART Framing Error Boolean Read This signal indicates that the received byte being output on UART Read Data did not have a valid stop bit. This means that a transmission error occurred and that the received data may not be reliable.
UART RX Overrun Error Boolean Read When this signal rises, it means that the receive buffer has filled and one or more bytes of received data have been lost. This occurs when data is not read out from the UART quickly enough.

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