Advanced Code Generation Page (FPGA I/O Node Properties Dialog Box)

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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Requires: FPGA Module

Select Advanced Code Generation in the Category list of the FPGA I/O Node Properties dialog box to display this page.

Use this page to select code generation options, such as the number of synchronizing registers. Supported options, values, and defaults depend on the FPGA target and FPGA I/O you use. This page displays only the options and values supported for the selected FPGA I/O. Some FPGA targets and FPGA I/O nodes might not allow access to this page at all.

This page can contain the following option:

  • Number of Synchronizing Registers for Read—Specifies the number of synchronizing registers between the FPGA target hardware interface and the FPGA I/O Node executing on the FPGA target. The FPGA target hardware interface might be a physical I/O connector on the device or a connection to a section of the FPGA that contains circuitry designed by National Instruments.

    Each synchronizing register executes in one clock cycle. If you use the FPGA I/O Node outside a single-cycle Timed Loop, LabVIEW places one additional synchronizing register, or holding register, that attempts to hold the digital value constant for subsequent operations in the FPGA VI. These synchronizing registers are in addition to enable chain registers that are present outside of the single-cycle Timed Loop. If you use the FPGA I/O Node inside a single-cycle Timed Loop, LabVIEW does not add the additional register because logic inside a single-cycle Timed Loop executes every clock cycle. However, you must use caution when synchronizing I/O in single-cycle Timed Loops.
    Caution  Select 0 only if you also use component-level IP (CLIP) and the HDL code contains its own synchronization registers. Otherwise, you might introduce metastable data in the FPGA VI and experience unpredictable behavior.
    Supported options typically include the following:
    • Inherit from the Project Item—Specifies to use the number of synchronizing registers configured in the Advanced Code Generation page of the FPGA I/O Properties dialog box.
    • Auto—Specifies that LabVIEW uses the default number of synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA. The following table lists the number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.

      LocationSynchronizing RegistersEnable Chain Register
      Inside an SCTL20
      Outside an SCTL11
    • 0—Specifies that LabVIEW does not place any synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA. Do not select this option for most FPGA Module applications.

      Note  If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.
      The following table lists the total number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.

      LocationSynchronizing RegistersEnable Chain Register
      Inside an SCTL00
      Outside an SCTL11
    • 1—Specifies that LabVIEW place one synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA.

      Note  You might encounter metastable data if the FPGA I/O Node is in a single-cycle Timed Loop and set with this option when the data is not already synchronized to the clock of the single-cycle Timed Loop.
      The following table lists the total number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.

      LocationSynchronizing RegistersEnable Chain Register
      Inside an SCTL10
      Outside an SCTL21
    • 2—Specifies that LabVIEW place two synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA. Select this option to avoid metastability if the value of the input to the FPGA I/O Node read element might change while the FPGA I/O Node samples the FPGA target hardware interface. If you select this option for an FPGA I/O Node within a single-cycle Timed Loop, you have no metastable data in the FPGA VI. The following table lists the total number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.

      LocationSynchronizing RegistersEnable Chain Register
      Inside an SCTL20
      Outside an SCTL31

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