Glossary

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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Prefixes

Symbol Prefix Value
M mega 10 6
k kilo 10 3
G giga 10 9

A

ADCAnalog-to-digital converter
APIApplication programming interface, such as LabVIEW or LabWindows.

B

base clockA digital signal in the hardware that you can use as a clock for an FPGA application.

C

CLIPComponent-level intellectual property. See user-defined CLIP and socketed CLIP.
CPTRCommon periodic time reference — a signal that defines the rate at which each device evaluates triggers.

D

DACDigital-to-analog converter
DCMDigital clock manager
DDRDouble data rate
DIODigital input/output
DRAMDynamic random access memory — LabVIEW supports two types of DRAM interfaces: FPGA memory items and socketed CLIP.

E

EEPROMElectrically Erasable Programmable Read-Only Memory

F

FAMFlexRIO adapter module
FIFOFirst In, First Out — A memory interface in which the first data to be added to the queue is the first data to be removed, and the last data added is the last to be removed.
Flip-flopA circuit with two stable states that can store state information.
FPGAField-programmable gate array

G

GPIOGeneral-purpose I/O

H

HDLHardware-description language — Language that describes a circuit's operation, design, and organization.

I

I2CInter-Integrated Circuit

L

LLBLabVIEW file that contains a collection of related VIs for a specific use.
LUTLook-up table - An array of values in which each value is assigned a key that can be used to look up the value.
LVDSLow-voltage differential signaling

M

MAXMeasurement & Automation Explorer — Configures National Instruments hardware and software.

P

P2PPeer-to-peer
PCIPeripheral component interconnect — A high–performance expansion bus architecture originally developed by Intel to replace ISA and EISA. It has achieved widespread acceptance as a standard for PCs and workstations, and offers a theoretical maximum transfer rate of 132 Mbytes/s. Future versions of the bus will be 64-bits wide and offer double-clock speed.
PFIProgrammable Function Interface — I/O channels to the digital waveform generator/analyzer. Functionality and specifications will vary by device and operation.
PLLPhase-locked loop — An electronic circuit which forces an output frequency to be locked to the same phase as a reference frequency.
PXIPPCI eXtensions for Instrumentation—Rugged, open system for modular instrumentation based on CompactPCI, with special mechanical, electrical, and software features.
PXI Express (PXIe)PCI Express eXtensions for Instrumentation — The PXI implementation of PCI Express, a scalable full-simplex serial bus standard that operates at 2.5 Gbps and offers both asynchronous and isochronous data transfers.

R

readerThe terminus of the unidirectional data stream. The reader reads data from the stream.

S

SEsingle-ended
socketed CLIPAllows your IP to communicated directly with circuitry external to the FPGA, such as the FPGA VI and the external adapter module connector interface.
SPISerial peripheral interface - A serial data link standard that allows simultaneous communication in both directions.

U

UARTUniversal Asynchronous Receiver/Transmitter
user-defined CLIPAllows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.

W

writerThe origin of the unidirectional data stream. The writer writes data to the stream.

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