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Memory Overview

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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Use the Memory instrument design library to access DRAM and BRAM on the device in a consistent manner. This library provides a basic read and write interface to DRAM and BRAM. This library supports LabVIEW FPGA data widths that are 128 bits and 64 bits wide for DRAM and BRAM, respectively. This instrument design library contains LabVIEW FPGA VIs.

In addition to the basic memory interface, you can use this instrument design library to reset the DRAM or BRAM. When memory read operations are posted to memory, there is some amount of latency before the associated data is retrieved from memory and presented to the FPGA diagram. Furthermore, multiple read operations can be queued up at once. You can use the Memory instrument design library to reset those queued memory operations.

This instrument design library also adds support for arbitration between the read and write ports of DRAM. Because the physical DRAM interface has a single port for read and write operations, the FPGA must arbitrate between reads and writes when accessing DRAM. This instrument design library implements a simple timeslice arbiter that provides for configurable bandwidth between the read and write ports. You can use this arbitration to achieve improved throughput with your DRAM read and write operations.

Refer to the LabVIEW context help of the Memory Design VIs for more information about the library interface.


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