Memory items that are assigned to the same bank cannot access the DRAM simultaneously. Access to the DRAM is controlled by a grant time that dicatates when a memory item can read or write to the DRAM bank, and for how long. By default, a DRAM bank assigns grant times of 50 cycles per memory item. You can modify the grant times in the DRAM Properties page of the FPGA target.
|Note You must configure grant times at compile time; grant times cannot be modified during run time.|
The ideal number of memory items per bank is 1. Having more than one memory item per bank prevents either item from accessing the DRAM with the most efficient bandwidth and latency, since memory items have to share access to the DRAM as dictated by the grant time.