User-Defined Variable

NI-Industrial Communications for EtherCAT® 17.6 Help

Edition Date: November 2017

Part Number: 372626P-01

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User-defined variables transfer custom FPGA-processed data between an FPGA VI and an RT VI.

Note Note  On the NI 9144/9145, you can transfer data between the FPGA targets and the real-time targets only by using user-defined variables. Refer to the LabVIEW Help for more information about transferring data between the FPGA target and the host on an RT local chassis.

You can add user-defined I/O variables to the block diagrams of FPGA VIs and RT VIs running on the target to communicate between the FPGA on the NI 9144/9145 and host real-time target. However, because all I/O variables are unidirectional, you must configure the direction of each user-defined I/O variable as either FPGA to Host or Host to FPGA. For example, you can acquire analog I/O data and perform an FFT on the data in an FPGA VI, use an FPGA to Host I/O variable to transfer the processed data to a control loop in an RT VI, then use a Host to FPGA I/O variable to transfer output data from the RT control loop back to the FPGA for output to the physical I/O channel.

Note Note  Refer to the LabVIEW Help for more information about the user-defined I/O variables.

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