List of PCL Execution Steps

NI VeriStand 2018 Help

Edition Date: May 2018

Part Number: 372846M-01

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The Primary Control Loop (PCL) controls the timing of the VeriStand Engine by performing several execution steps. The PCL can run in one of two modes, where the only difference between the modes is the timing of model-related steps:

  • In Parallel mode, the PCL initiates execution of models and continues to its next iteration without waiting for models to finish executing. This causes a one-cycle delay between when a model starts executing and when the data it produces is available to the system.
  • In Low Latency mode, the PCL waits for the Model Execution Loop(s) to finish executing, and then reads and publishes model values to the system during every iteration of the system.

Related Link

Understanding PCL Execution and Model Latency

Understanding the VeriStand Engine

PCL Execution in Parallel Mode

The PCL takes the following steps in Parallel mode. Notice that step 4 results in a one-cycle delay between when a model executes and when the data it produces is available to the system.

  1. Gets inputs from hardware devices in the system definition.
    Note  If the system includes an inline hardware interface custom device, the PCL reads DAQ digital lines and counters after the Read Data from HW case of the custom device executes in step 3.
  2. Reads asynchronous custom device FIFOs from the previous iteration.
  3. Runs the Read Data from HW case of inline hardware interface custom devices. If you configured hardware scaling, NI VeriStand applies the scaling after acquiring all hardware inputs.
  4. (Second and subsequent iterations) Reads previous iteration data from models in the system definition.
  5. Reads data from the previous iteration of the Data Processing Loop.
  6. Processes system mappings.
    Note  VeriStand components (including custom devices) cannot read data from a previous step until the PCL processes system mappings, even if the previous step acquired the data the component needs.
  7. Runs the Execute Model case of inline model interface custom devices.
  8. Executes steps of running real-time sequences.
    Note  VeriStand executes real-time sequences after input operations but before output operations and continues to run every step of the real-time sequence until the sequence is complete, reaches a Yield step, or completes an iteration of a loop with Auto Yield set to TRUE. If a sequence takes longer than the given time for an iteration of the PCL, the PCL runs late. To avoid errors, break up the timing of the steps by placing Yield steps throughout the sequence and enabling the Auto Yield property for any loops in the sequence.
  9. Processes system mappings.
  10. Writes data to the Data Processing Loop.
  11. Writes data to models.
  12. Initiates asynchronous execution of models.
  13. Writes output data to hardware devices.
  14. Runs the Write Data to HW case of inline hardware interface custom devices.
  15. Writes data to asynchronous custom device FIFOs.

PCL Execution in Low Latency Mode

The PCL takes the following steps in Low Latency mode as it transfers data to and from a model. Note that the PCL waits for the model to finish executing (step 9) before it continues to execute. When the model completes execution, the PCL provides data from the model to other loops during the same iteration that the model generated the data.

Note  National Instruments recommends you select this mode only if you need to minimize the latency between your inputs, model execution, and outputs. Waiting for Model Execution Loops to read, execute, and write on each iteration can significantly slow the execution speed of the system.
  1. Gets inputs from hardware devices in the system definition.
    Note  If the system includes an inline hardware interface custom device, the PCL reads DAQ digital lines and counters after the Read Data from HW case of the custom device executes in step 3.
  2. Reads asynchronous custom device FIFOs from the previous iteration.
  3. Runs the Read Data from HW case of inline hardware interface custom devices. If you configured hardware scaling, VeriStand applies the scaling after acquiring all hardware inputs.
  4. Reads data from the previous iteration of the Data Processing Loop.
  5. Processes system mappings.
    Note  VeriStand components (including custom devices) cannot read data from a previous step until the PCL processes system mappings, even if the previous step acquired the data the component needs.
  6. Runs the Execute Model case of inline model interface custom devices.
  7. Executes steps of running real-time sequences.
    Note  VeriStand executes real-time sequences after input operations but before output operations and continues to run every step of the real-time sequence until the sequence is complete, reaches a Yield step, or completes an iteration of a loop with Auto Yield set to TRUE. If a sequence takes longer than the given time for an iteration of the PCL, the PCL runs late. To avoid errors, break up the timing of the steps by placing Yield steps throughout the sequence and enabling the Auto Yield property for any loops in the sequence.
  8. Processes system mappings.
  9. Writes data to models.
  10. Initiates execution of models and waits for them to complete execution.
  11. Reads data from models.
  12. Processes system mappings.
  13. Writes data to the Data Processing Loop.
  14. Writes output data to hardware devices.
  15. Runs the Write Data to HW case of inline hardware interface custom devices.
  16. Writes data to asynchronous custom device FIFOs.

Related Links

Inline Hardware Interface Custom Devices

Asynchronous Custom Devices

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