NI cRIO-FRC II

NI-RIO Software Help 4.0

Edition Date: August 2011

Part Number: 373197B-01

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CompactRIO 4-Slot, 1 M Gate FPGA, 256 MHz Real-Time Integrated Controller and Chassis

NI cRIO-FRC II Front Panel

Writing to DMA FIFOs on the NI cRIO-FRC II

Keep in mind the following guidelines for writing to DMA FIFOs on the NI cRIO-FRC II:

• Always check the Empty Elements Remaining indicator from any previous DMA write operation before doing the next DMA FIFO write.
• The DMA engine transfers data in 64-byte chunks. If the host FIFO is full, reading data in amounts that are non-multiples of 64 bytes from either the FPGA FIFO or the host FIFO does not necessarily free an equivalent amount of space on the other FIFO.
• The DMA host FIFO size is limited to 2,096,960 bytes.

Refer to the Best Practices for Using DMA FIFOs (FPGA Module) topic for more information about DMA FIFOs.

Hardware Documentation

Refer to the CompactRIO cRIO-FRC II Operating Instructions and Specifications to learn about controller specifications and how to use the controller. Refer to the C Series Related Documentation for further information about CompactRIO documentation.