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FPGA IP Builder Concepts (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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The LabVIEW FPGA IP Builder enables you to create FPGA algorithms, interactively optimize the algorithms according to specific application requirements, and automatically generate efficient LabVIEW FPGA code.

Note  You must have the LabVIEW FPGA Module, necessary Xilinx compilation tools, and NI-RIO installed on the local computer to use the FPGA IP Builder. Refer to the FPGA Module installation options on the LabVIEW Platform DVD, or your original media, for instructions on installing the FPGA Module and Xilinx compilation tools for LabVIEW. Refer to the NI Device Drivers DVD for instructions on installing NI-RIO.

After you install the FPGA IP Builder, an IP Builder project item automatically appears when you add an FPGA target to a LabVIEW project. The FPGA IP Builder supports only a limited number of FPGA targets. Refer to the LabVIEW FPGA IP Builder Readme for information about supported FPGA targets.

Advantages of the FPGA IP Builder

In traditional LabVIEW FPGA programming, you create an FPGA VI and compile the VI on an FPGA target to verify whether this VI meets specific application requirements, such as a high throughput at a high clock rate. If the VI does not meet specific application requirements, you must learn FPGA hardware knowledge, modify the algorithm, and compile the VI again. Compiling FPGA VIs is time consuming. This trial-and-error process also requires a lot of iterations and is challenging without sufficient FPGA hardware knowledge.

After you finalize the FPGA VI, you usually cannot reuse the same VI in other applications that have different requirements on timing performance or resource usage. You must modify the VI and repeat the whole programming process to accommodate the different requirements. Compared with traditional LabVIEW FPGA programming, the FPGA IP Builder has the following advantages:

  • The FPGA IP Builder can estimate the performance and device utilization of the algorithm VI without compilation. This estimation process requires less time than traditional FPGA compilation process.
  • The FPGA IP Builder provides a number of directives for you to optimize the algorithm VI. You can configure the directives and then estimate the performance and device utilization conveniently.
  • The FPGA IP Builder enables you to reuse algorithm VIs in different FPGA applications. You can apply different optimization options to the same algorithm VI to obtain different performance.
  • The FPGA IP Builder returns efficient LabVIEW FPGA code according to the optimization options you configured. You can use the LabVIEW FPGA code with other LabVIEW FPGA VIs and functions conveniently.

 

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