Creating Algorithm VIs (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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The first step in the FPGA IP design process is to create algorithm VIs. Algorithm VIs describe the behavior of the FPGA IP you want to generate. You must create these VIs under the IP Builder project item in the Project Explorer window. Right-click the IP Builder project item and select New»VI from the shortcut menu to create an algorithm VI.

You can also add existing algorithm VIs to a LabVIEW project. Right-click the IP Builder project item and select Add»File from the shortcut menu to add existing algorithm VIs.

Note  The LabVIEW FPGA IP Builder supports only a limited number of data types and functions. Therefore, the algorithm VIs might be broken if you directly add them to the IP Builder project item. When you find a broken algorithm VI, modify the VI to use appropriate data types and functions.

You can use 12 terminals at most on the connector pane of the top-level algorithm VI. LabVIEW returns errors when you create a directives item from a VI that has more than 12 connector pane terminals.

Use the following guidelines when creating an algorithm VI:

Note  These guidelines are subject to change with each version of the FPGA IP Builder.
  • Use an appropriate word length and integer word length for fixed-point numbers and operations. Using a word length that is too large might negatively affect the timing performance and device utilization of the resulting FPGA IP.
  • The FPGA IP Builder does not support subnormal floating-point numbers. Subnormal floating-point numbers result in values of 0. This behavior leads to some small differences in calculations when compared to results you obtain according to the IEEE 754 standard. The maximum deviation in results compared to IEEE 754 is 2–126.
  • If you are processing an array, avoid branching the wire that comes from this array to two or more destination functions that modify the content of the array. Using wire branches might result in another copy of the same array, and copying an n-element array might take n additional cycles.
  • If you are processing an array, avoid coercion dots. Coercion dots alert you that LabVIEW converted the value passed into the node to a different representation. When converting the value, LabVIEW might use additional computational resources and time. For example, if a coercion dot appears when you wire an array to a numeric function, LabVIEW uses additional cycles to convert each element of the array to proper representation.
  • If the block diagram contains parallel execution of two or more loops, move each loop into a subVI and enable the inline off directive for each subVI. Moving loops into subVIs optimizes parallel implementation of the algorithm VI.
  • Front panel controls and indicators wired to the connector pane of the top-level VI might require additional resources. Clean up the front panel by removing unused controls or indicators. If the front panel contains indicators that are wired to the connector pane and used for debugging purposes only, remove these indicators after you finish debugging the VI.
  • If you are processing data in a While Loop, avoid wiring a front panel Boolean control to the conditional terminal. Instead, modify your algorithm to programmatically stop the While Loop. Using front panel Boolean controls to stop a While Loop might cause the generated FPGA IP to run infinitely.
  • LabVIEW by default uses the Saturate mode and the Round-Half-Even mode, respectively, to handle overflow and rounding. However, the default modes require additional FPGA resources. In the algorithm VI, you can use the Wrap mode and the Truncate mode to reduce hardware resource usage.


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