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Estimating Device Utilization and Performance (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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After you configure directives for an algorithm VI, estimate the device utilization and performance of the configurations. If the estimation result does not meet the requirements you need, adjust the directive configurations until the estimation result is satisfactory.

When you estimate the device utilization and performance, you have the option to choose a Quick estimate or a Thorough estimate from the Estimates page of the Directives Properties dialog box. The Quick estimate provides you with a faster estimation of device utilization, including slice registers, slice LUTs, DSP48s, and block RAMs, and performance, including clock rate, initiation interval, pipeline type, minimum latency, and maximum latency. The Thorough estimate provides a more accurate device utilization estimate through a Xilinx ISE compilation, as well as an estimate of the number of total slices, but takes longer than the Quick estimate.

Note  The estimation reports do not include the routing delays that might happen during FPGA compilation. Therefore, only use the estimation reports as a reference. The estimation reports for a large algorithm VI might be less accurate than those for a small algorithm VI. In some cases, the generated FPGA IP might encounter timing violations when you compile the FPGA IP at the estimated clock rate.

Understanding the Estimation Reports

You can read each report on the Estimates page after the report becomes available. Use the information in the reports to determine whether the directive configurations meet the performance and device utilization requirements. You can find the following reports from the Reports pull-down menu.

  • Summary—Provides an overview of the estimation result and is available only when the estimation is complete.
  • Design Feedback—Provides feedback on the algorithm VI and directives you set. You can use this design feedback to improve your IP design and performance. The Design Feedback report lists warnings and useful information for your IP design.
  • Configuration—Provides project information and the directives information you specify on the General page.
  • Quick Device Utilization Estimate—Available only when the Quick estimate is complete. This report includes the following information:
    • Device Utilization—Indicates the FPGA elements, such as Slice Registers, Slice LUTs, block RAMs, and DSP48s.
    • Quick estimate—Indicates a quick estimate of the number of FPGA elements the algorithm might use based on the current directive configurations.
    • Total—Indicates the total number of FPGA elements available on the FPGA target.
    • Percent—Indicates the percentage of the FPGA elements that the algorithm might use according to the quick estimate.
  • Quick Performance Estimate—Available only when the Quick estimate is complete. This report includes the following information:
    • Type—Indicates the directive names of the estimated performance. This report also includes Pipeline type, which has one of the following values:
      • Not pipelined—Indicates that the FPGA IP is not a top-level pipelined design. You might get this type if you do not configure the Initiation interval directive of the top-level VI, or if you configure this directive but the FPGA IP Builder fails to pipeline the top-level VI.

        Compared with the other two types, this type uses the fewest resources but provides the lowest throughput.
      • Fully pipelined—Indicates that the FPGA IP is a top-level pipelined design. This type of design can achieve an initiation interval of 1 cycle.

        Compared with the other two types, this type provides the highest throughput but requires the maximum number of resources. When an FPGA IP is fully or partially pipelined, the Maximum latency in the estimation reports equals the Minimum latency.
      • Partially pipelined—Indicates that the FPGA IP is a top-level pipelined design. This design can achieve an initiation interval of 2 cycles or more.

        Compared with the other two types, this type balances between resource usage and throughput. When an FPGA IP is fully or partially pipelined, the Maximum latency in the estimation reports equals the Minimum latency.
    • Requested—Indicates the value you specified for the directive.
    • Quick estimate—Indicates a quick estimate of the value for the directive based on the current configurations.
  • Thorough Estimation Results—Available only when the Thorough estimate is complete. This report includes the following information:
    • Type—Indicates the directive names of the estimated performance.
    • Requested—Indicates the value you specified for the directive.
    • Quick estimate—Indicates a quick estimate of the value for the directive based on the current configurations.
    • Thorough estimate—Indicates a thorough estimate of the value for the directive based on the current configurations.
  • Log—You can use this report to troubleshoot estimation failures.

Resolving Problems in the Estimation Reports

Estimating the performance of the directive configurations is an iterative process. If the estimation reports do not meet the application requirements, optimize the directive configurations on the Directives page of the Directives Properties dialog box and run the estimation again. The following are typical problems that you might encounter in the estimation reports and possible solutions.

Note  Before applying the possible solutions, you must ensure that the algorithm VI conforms to the guidelines.
  • Problem: Estimated latency or initiation interval in the reports does not meet the minimum application requirement.

    Possible solutions:
    • Configure the Initiation interval directive of the top-level VI to match the throughput you want to achieve. Configuring this directive might also improve the latency performance. However, this solution might require more computational resources.
    • If you use loop structures in the algorithm VI, configure the Initiation interval and Unroll factor directives of the loop. Pipelining loops enables LabVIEW to start the next loop iteration as early as possible, even before completing the current iteration, which can reduce the latency of the whole loop execution. Unrolling loops enables LabVIEW to duplicate the loop operations in one iteration, which can reduce the number of loop iterations.
    • Configure the Partition type directive of small-size arrays to use the Complete option. Array operation affects the throughput and latency greatly. Partitioning small-size arrays into individual elements might improve the throughput of the entire algorithm. If you want to use other partition types, configure the number of partitions properly to access multiple array elements simultaneously.
    • If you use subVIs in the algorithm VI, configure the Inline subVIs and Inline self directives to inline subVIs into the caller VI, which can reduce the clock cycle overhead of calling subVIs.
  • Problem: Estimated clock rate does not meet the minimum application requirement.

    Possible solutions:
    • Check the Quick Performance Estimate report to identify subVIs that do not meet the minimum clock rate requirement. Configure the directives of the subVIs or modify the subVIs to improve the clock rate.
    • Specify a Clock rate value higher than the required clock rate for your application.
    • Configure the Number of pipeline stages directive of the Multiply functions in the algorithm VI to use a greater value.
  • Problem: Estimated device utilization does not meet the minimum application requirement.

    Possible solutions:
    • If the estimated usage of DSP48 slices exceeds the maximum number of available resources on the corresponding FPGA target, place a checkmark in the Share multipliers directive checkbox of the top-level VI.
    • If the estimated usage of block RAM exceeds the maximum number of available resources on the corresponding FPGA target, configure the Resource directive of arrays to use LUT RAM or ROM.
    • If you configured the Initiation interval directive of a VI, disable this directive and configure the Unroll factor directive of the loop structures inside the VI instead.
    • If you configured the Unroll factor directive to unroll loop structures, disable this directive and configure the Initiation interval directive of the owning VI instead.
    • Investigate the Block Diagram Components list on the Directives page to identify all instances of Array Buffer. Modify the algorithm VI to reduce the number of array buffers.
    • Avoid using the Complete option to partition arrays.
    • If you used a subVI in multiple locations of the algorithm VI, inlining this subVI might require a lot of hardware resources. Enable the Inline off directive of this subVI to improve resource usage.

 

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