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Latency Optimization (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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In the LabVIEW FPGA IP Builder, latency of an FPGA IP refers to the number of cycles the FPGA IP needs to complete one iteration of the original algorithm VI. The FPGA IP Builder estimates the latency based on the assumption that the input data of the FPGA IP are always ready when this FPGA IP requests new input data. You can change the latency of an FPGA IP by configuring the directives, such as Minimum latency and Maximum latency.

Note  Changing any other directive, such as Initiation interval, might also affect the latency.

Even with the same set of directive configuration, an FPGA IP might have different latency values, depending on how the FPGA IP processes the input data. For example, if the algorithm VI contains a Case structure, the different cases in this structure might require different numbers of cycles to complete execution. The FPGA IP Builder calculates the Minimum latency and Maximum latency values in the estimation reports to help you obtain knowledge about the lower limit and upper limit of the latency of an FPGA IP.

Note  The Minimum latency and Maximum latency values in the estimation reports are estimated values only. When you use the generated FPGA IP in a real-world FPGA application, the actual latency between the input valid and output valid of the FPGA IP might be different from the estimated value. If you want to synchronize the FPGA IP with other FPGA code running in parallel, National Instruments recommends that you either use handshaking signals of the FPGA IP or use the actual latency. If you use the actual latency to synchronize the FPGA IP with other FPGA code running in parallel, you must have sufficient knowledge about how the FPGA IP processes the input data. Obtaining such knowledge is challenging especially when the FPGA IP uses element-by-element interface directives.

The LabVIEW FPGA Module defines latency as the number of cycles between input valid and output valid, or the cycles between the inputs and outputs. However, when estimating the latency values, the FPGA IP Builder takes the entire algorithm into account, including the code that updates the internal states. For example, the following figure shows the block diagram of an FIR transposed digital filter:

The circled code updates the internal states, which is not related to the output y. The FPGA IP Builder also takes this code into account when estimating the latency of the generated FPGA IP. Therefore, the actual latency between x and y, or the latency defined by the FPGA Module, is much less than the latency estimated by the FPGA IP Builder. If you rely on the estimated latency to synchronize the FPGA IP with other FPGA code running in parallel, you might get unexpected results.

Different Latency Values in the Element-by-Element Interface

If you configure an FPGA IP to use an element-by-element interface directive, the FPGA IP might have different latency values when you use this FPGA IP in a real-world application. For example, you have an FPGA IP with the following inputs and outputs:

This FPGA IP calculates the dot product of X and Y and the product of a and X, where X and Y are 10-element arrays and a is a scalar. The following figure shows the front panel of this FPGA IP:

In the interface of this FPGA IP, X and Y use the Element-by-element, unbuffered interface directive and a * X uses Element-by-element, buffered. The Boolean control input valid becomes TRUE when the next data point of a has arrived for processing. The Boolean indicator output valid becomes TRUE when the current data point of X * Y is valid and ready to be used by downstream nodes. Each element of X, Y, and a * X has its own valid? control or indicator. If the array elements of X and Y are always available for the FPGA IP, the latency is 31 cycles, as shown in the following figure:

In the previous figure, the first input is available when Time equals 1 and the last output is available when Time equals 32. Therefore, the latency of this FPGA IP is 31 cycles.

Note  Although the output valid plot becomes TRUE when Time equals 20, the output values for a * X are not available until Time equals 32. In this example, you cannot use the output valid plot to calculate the latency of the FPGA IP.

If the array elements are not always available for the FPGA IP, the latency value might be greater than 31. In the following figure, the array elements are available in every other cycle, so the FPGA IP takes longer than the previous example to process the input data. The first input is available when Time equals 1 and the last output is available when Time equals 41, so the resulting latency of this FPGA IP is 40 cycles.

In the previous example, if the input data are ready randomly, you might get different latency values every time you run the FPGA IP. National Instruments recommends that you always use handshaking signals of an FPGA IP to synchronize the FPGA IP with other FPGA code running in parallel.


 

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