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Loop Optimization (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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You can configure the following directives for a For Loop or While Loop in the algorithm VIs. These directives appear when you select a loop structure from the Block Diagram Components list on the Directives page of the Directives Properties dialog box.

  • Unroll factor—Specifies the factor to use to unroll a loop structure. Unrolling loops enables LabVIEW to duplicate the loop operations in one iteration, potentially increasing parallelism. However, unrolling loops requires additional hardware resources.
    Note  Specifying a value for the Initiation interval of a VI completely unrolls all loop structures within the hierarchy of this VI. However, if you specified a value for the Unroll factor directive of one of the loop structures and the value is smaller than the corresponding loop iteration count, LabVIEW does not completely unroll this loop structure.
  • Initiation interval—Specifies the number of cycles between the start of two iterations of the loop structure. This directive recursively unrolls all loop structures nested in the current loop structure.
  • Minimum latency—Specifies the minimum number of cycles between the start and finish of one loop iteration. Configuring the Minimum latency and Maximum latency directives can impact the latency of the FPGA IP.
  • Maximum latency—Specifies the maximum number of cycles between the start and finish of one loop iteration. Configuring the Minimum latency and Maximum latency directives can impact the latency of the FPGA IP.

Reducing the Number of Buffer Loops

After you estimate the device utilization and performance, you might find one or more items with the name BufferLoop in the Quick Performance Estimate report. Buffer loops are loop structures that LabVIEW automatically generates to copy arrays or create array buffers. These loops affect the Initiation interval and latency of the resulting FPGA IP because they require additional computational time. You might be able to reduce the number of buffer loops from the estimation reports by modifying the algorithm VI. For example, you can avoid branching the wire that comes from an array.


 

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