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VI Optimization (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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When you optimize an FPGA IP design, the first step is to configure the directives of the algorithm VIs and the interface of the top-level VI. These directives are basic items and affect the overall performance of the resulting FPGA IP. On the Directives page of the Directives Properties dialog box, select the top-level VI, any subVI, or Interface from the Block Diagram Components list to view the directives you can configure for each category.

Configuring Interface Directives

Interface directives are items you can configure for the inputs and outputs of the top-level VI. You must connect the inputs and outputs to the terminals of the connector pane; otherwise the inputs or outputs do not appear under the Interface category. Before configuring the interface directives, ensure the interface is compatible with the application for which you want to use the generated FPGA IP.

You can categorize the inputs and outputs of the top-level VI into two data types: arrays and scalars. Different options are available for different data types. If the data type is a scalar, LabVIEW provides the following option:

  • Data—Processes the input data or output data in one cycle.

If the data type is an array, LabVIEW provides the following options:

  • All elements—Processes all elements of the array in one cycle. LabVIEW uses registers to store all the array elements. Use this option when you want to process a small-size array or need to access all array elements simultaneously.
    • Pros: This option can access all elements at one cycle and does not require memory resources on FPGA targets.
    • Cons: This option might not work for large-size arrays because registers are limited resources on FPGA targets.
  • Element-by-element, buffered—Processes only one element of the array at each cycle. LabVIEW stores the array elements in an internal buffer. Use this option when you want to access the array elements randomly in the algorithm VI. This is the default option LabVIEW uses for all arrays on the interface of the top-level VI.
    • Pros: This option works for large-size arrays, and you can access the array elements randomly.
    • Cons: This option can access only one element at each cycle and requires memory resources to store the array elements. This option therefore requires one cycle per array element to buffer the array elements before you can access them randomly.
  • Element-by-element, unbuffered—Processes only one element of the array at each cycle. LabVIEW does not store the array elements in an internal buffer. Use this option only when you want to access every array element in the algorithm VI sequentially.
    Note  National Instruments recommends that you use this option to process only the array in a loop structure of the top-level VI, by wiring the array to the loop structure through auto-indexed loop tunnels. Avoid branching the wire that comes from the array.
    • Pros: This option works for large-size arrays. Compared with the Element-by-element, buffered option, this option does not require memory resources. This option also requires fewer cycles, because LabVIEW does not buffer the array elements in advance.
    • Cons: This option can access only one element at each cycle. You must access all array elements sequentially. LabVIEW might return errors if you use this option and your algorithm VI does not process all array elements sequentially.

Configuring Directives for the Top-Level VI and subVIs

Directives for the top-level VI affect the implementation of the entire algorithm. You can configure the following directives for the top-level VI and subVIs:

  • Clock rate—This directive is for the top-level VI only. Specifies the clock rate, in MHz, you want to achieve for the overall FPGA IP design. This directive is required for all FPGA IP. The default value is 40 MHz.
  • Share multipliers—This directive is for the top-level VI only. Specifies whether you want to implement the algorithm by sharing multipliers. Sharing multipliers enables the resulting FPGA IP to use fewer DSP48s but might require more logical resources, such as multiplexers. A multiplexer, also known as a mux, is a circuit that selects between two or more inputs and then outputs the selected input. Multiplexers can increase latency and negatively affect the timing performance of the FPGA IP.

    To share multipliers, place a checkmark in this checkbox and select True from the Value pull-down menu. To stop sharing multipliers, remove the checkmark from this checkbox or select False from the Value pull-down menu.
  • Initiation interval—Specifies the number of cycles between new data inputs to the VI. This directive recursively unrolls all loop structures in the current VI and the subVIs to achieve the specified Initiation interval. You can specify different values for the Initiation interval of a subVI and its caller VI. If you do not specify a value for the Initiation interval of a subVI, then the subVI inherits the Initiation interval of its caller VI.

    If the input of the VI is a scalar and you want the VI to run at an input sampling rate of fs samples per second, the maximum value for the Initiation interval is floor(Clock rate/fs). If the input is an array containing m elements and the VI processes the array element-by-element at an input sampling rate of fs elements per second, the maximum value for the Initiation interval is floor(Clock rate/fs)*m.
  • Minimum latency—Specifies the minimum number of cycles between the start and finish of one execution of the VI. The Minimum latency and Maximum latency directives have a lower priority than other directives. Configuring the Minimum latency and Maximum latency directives can impact the latency of the FPGA IP.
  • Maximum latency—Specifies the maximum number of cycles between the start and finish of one execution of the VI. The Minimum latency and Maximum latency directives have a lower priority than other directives. Configuring the Minimum latency and Maximum latency directives can impact the latency of the FPGA IP.
  • Inline subVIs—Specifies whether you want to inline subVIs into the current VI. When you call a subVI, a certain amount of clock cycle overhead is associated with the call. Inlining the subVI can minimize this overhead. When you inline a subVI, LabVIEW executes the subVI code inside the compiled code of the caller VI. Inlining subVIs is most useful for small subVIs, subVIs within a loop, subVIs with unwired outputs, or subVIs you call only once. LabVIEW automatically inlines small subVIs into the caller VI, even if this option is disabled.

    To inline subVIs, place a checkmark in this checkbox and select True from the Value pull-down menu. To stop inlining subVIs, remove the checkmark from this checkbox or select False from the Value pull-down menu.
    Note  If you use a subVI in multiple locations of the algorithm VI, inlining this subVI might require a lot of hardware resources. You can enable the Inline off directive for this subVI to improve resource usage.

    Configuration of this directive is valid only if the corresponding VI has subVIs and the Inline off directive of each subVI is disabled.
    • Inline recursively—Specifies whether you want to inline the subVIs in the current VI recursively.
  • Inline self—Specifies whether you want to inline the current VI to the caller VI. This directive is for subVIs only. Use this directive to improve the latency and initiation interval when the current VI has a small size.
    Note  The configuration of this directive takes precedence over the Inline subVIs directive of the caller VI. LabVIEW ignores this directive if Inline off of the same VI is TRUE.
  • Inline off—Specifies whether you want to disable inlining of the current VI to the caller VI. This directive is for subVIs only. Use this directive to reduce hardware resource usage when the current VI requires a lot of resources and exists in multiple locations of the caller VI.
    Note  The configuration of this directive takes precedence over the Inline self directive of the same VI and the Inline subVIs directive of the caller VI.

 

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