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Optimizing an FPGA IP Design (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

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After you create a directives item from your algorithm VI, you can configure the directives to optimize the performance of the resulting FPGA IP. Even if you do not make any configurations to the directives before generating FPGA IP, the LabVIEW FPGA IP Builder still applies the following default optimization tasks:

  • Inlining small-size subVIs to the caller VI.
  • Applying constant folding to operations that use scalar or array constants.
  • Converting operations to logical shifts to reduce device utilization on FPGA. For example, if the algorithm VI has a calculation of ax8, the FPGA IP Builder converts this operation to a<<3.
  • Determining an appropriate value for the Number of pipeline stages directive of all Multiply functions in the algorithm VI.
  • Partitioning small-size arrays into individual numeric numbers and storing them in registers instead of memory.

This book contains information that helps you configure the directives to achieve optimal performance of the resulting FPGA IP.


 

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