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This book contains step-by-step instructions to help you get started using the LabVIEW FPGA IP Builder. This tutorial assumes you have fundamental knowledge about designing digital filters and using the LabVIEW FPGA Module. In this tutorial, you design a 15-tap fixed-point FIR filter and then generate FPGA IP from this digital filter.
This tutorial assumes you have a real-world FPGA application that runs on a PXI-7851R target. This application executes at a clock rate of 200 MHz. For this application, you need to create a 15-tap fixed-point FIR filter and this filter must process one new data sample in each cycle. The block diagram of the fixed-point filter looks like the following figure:
In the previous figure, you create a fixed-point Direct Form FIR filter with 15 taps. You can find this VI in the following path: labview\examples\FPGAIPBuilder\FIR\Algorithm\FIR.vi.
The VI you created in the previous section does not work with single-cycle Timed Loops because this VI contains a For Loop. If you want this VI to return a valid result in each clock cycle, you must rewrite the VI by manually unrolling the For Loop, which introduces redundant programming code. For example, manually unrolling the For Loop you created in the previous section might produce the following block diagram:
Refer to the labview\examples\FPGAIPBuilder\FIR\Algorithm\Manually_Unrolled_FIR.vi for a completed version of the VI that unrolls the For Loop.
By using the FPGA IP Builder, you do not have to manually unroll the For Loop. You can generate FPGA IP from the algorithm VI and then use the FPGA IP directly in the FPGA application. You can also customize the configurations of the FPGA IP to meet specific application requirements, such as the clock rate and initiation interval.
Complete the following steps to generate FPGA IP from the fixed-point FIR filter you created in the previous section.