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After you generate FPGA IP, you can run the FPGA IP to validate the function, initiation interval, and latency. You also can validate the clock rate and resource usage by including the FPGA IP in a single-cycle Timed Loop and generating a compilation report.
After you validate the generated FPGA IP, you can apply the IP to real-world FPGA applications. If you get unexpected results from the application running on the FPGA, you can debug the FPGA VIs. If you want to distribute the FGPA IP to other computers, you must also distribute the corresponding supporting files directory together with the FPGA IP.
|Note When you use the FPGA IP on FPGA targets, you must include the FPGA IP in a single-cycle Timed Loop. The VI containing the generated FPGA IP ignores inputs at the first cycle. After you compile and download this VI to an FPGA target, this VI initializes on the FPGA target only when you run this VI for the first time. Therefore, you might get different results when you run this VI after the first execution without re-downloading this VI.|
You can validate the function, initiation interval, and latency of the FPGA IP without compilation. Instead, you can validate the FPGA IP on the host computer. Complete the following steps to validate the FPGA IP.
Refer to the labview\examples\FPGAIPBuilder\Product\Validation\Product_Validation.vi for an example VI that you can use to validate the function, initiation interval, and latency of the FPGA IP.
Clock rate estimates provided by the Thorough estimate may be different from the clock rate achieved when you compile the IP within the whole application, depending on the size and complexity of the whole application. You must therefore validate the clock rate and resource usage of the FPGA IP by compiling the FPGA IP on an FPGA target. Complete the following steps to validate the clock rate and resource usage.
A successful compilation indicates that the FPGA IP can meet the clock rate requirement. In the compilation report, check the number of DSP48s and block RAM. After you validate the clock rate in the single-cycle Timed Loop, you also need to add the FPGA IP to a real-world FPGA application to verify that the whole application can compile at the expected clock rate.