LabVIEW 2013 FPGA IP Builder Help
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In Part 2 of this tutorial, you create a VI with the fixed-point FIR filter algorithm. In Part 3 of this tutorial, you create a directives item from this VI. You then configure the directives to ensure the algorithm meets the following specific application requirements:
- The fixed-point FIR filter must process one new data sample in each cycle, which means the initiation interval of the generated FPGA IP must equal 1 cycle/sample.
- The fixed-point FIR filter must execute at a clock rate of 200 MHz or higher.
After configuring the directives, you generate an estimation report to verify the timing performance and device utilization. You might need to adjust the directive configuration and estimate the result iteratively.
Creating a Directives Item
Complete the following steps to create a directives item from the fixed-point FIR filter.
- Open the project you saved in Part 2 of this tutorial.
- In the Project Explorer window, navigate to My Computer»FPGA Target (PXI-7851R)»IP Builder.
- Right-click FIR.vi and select Create Directives from the shortcut menu.
An item with the file name FIR directives appears above the VI you selected. Continue with the following section of this topic to configure this directives item.
Configuring a Directives Item
After you create a directives item, check the flowchart to understand how to configure the directives item. Complete the following steps to configure this directives item.
- Double-click FIR directives that you created in the previous section.
- In the FIR directives Properties dialog box that appears, click the Directives tab.
- Click through the items in the Block Diagram Components list. Corresponding directives appear in the Directives list as you click through the block diagram components.
- Select the top-level VI in the Block Diagram Components list.
- In the Directives list, make the following changes:
- Change the value of Clock rate from 40 to 200.
- Place a checkmark in the Initiation interval checkbox and verify the value is 1.
- On the Estimates page, click Quick estimate or Thorough estimate to generate an estimation report. In the estimation report summary, notice that the algorithm can compile at a clock rate greater than 200 MHz and requires only one cycle to process a new data sample.
- Click OK to save the directives item.
- Save the project.
After you verify in the estimation report that the directives item meets the application requirements, you can generate FPGA IP from this directives item in Part 4 of this tutorial.