Company Events Academic Community Support Solutions Products & Services Contact NI MyNI

Part 4: Generating FPGA IP from a Directives Item (FPGA IP Builder)

LabVIEW 2013 FPGA IP Builder Help

Edition Date: June 2013

Part Number: 373567C-01

»View Product Info
Download Help (Windows Only)

In Part 3 of this tutorial, you create a directives item for the fixed-point filter algorithm VI. You then configure the directives to make sure the algorithm meets specific application requirements. In Part 4 of this tutorial, you create build specifications from the directives item and then generate FPGA IP.

Creating Build Specifications

Complete the following steps to create build specifications from a directives item.

  1. Open the project you saved in Part 3 of this tutorial.
  2. In the Project Explorer window, navigate to My Computer»FPGA Target (PXI-7851R)»IP Builder.
  3. Right-click the FIR directives item and select Create IP Build from the shortcut menu.

    A project item with the same name FIR directives as the directives item you selected appears under IP Builder»Build Specifications.
  4. Double-click the new item to open the IP Build Specifications dialog box.
  5. On the Information page, verify the build specifications, such as the generated VI name and destination directory, and click OK.
  6. Save the project.

Generating FPGA IP

After you create build specifications from the directives item, complete the following steps to generate FPGA IP.

  1. Right-click the build specification item you created in the previous section and select Build from the shortcut menu.
  2. In the Build FPGA IP dialog box, view the build reports when they are available, and verify the report meets the application requirements.
  3. Click the Close button to close the Build FPGA IP dialog box.

    A folder with the name IP Builder Generated VIs appears under My Computer»FPGA Target (PXI-7851R). This folder contains the generated FPGA IP with the name FIR directives Generated.vi.
  4. Double-click the FIR directives Generated.vi to view the front panel and block diagram components. Notice that the generated FPGA IP contains three more terminals than the original fixed-point filter algorithm VI: input valid, output valid, and feedback signals. These terminals are necessary for passing handshaking signals in an FPGA application.
  5. Save the project.

After you generate FPGA IP, you can validate the FPGA IP in Part 5 of this tutorial.


 

Your Feedback! poor Poor  |  Excellent excellent   Yes No
 Document Quality? 
 Answered Your Question? 
Add Comments 1 2 3 4 5 submit